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32-bit risc microcontroller tx03 series TMPM372FWUG semiconduct or & storage products company

revision history date rev description 2011/8/1 1.0 first release 2013/4/15 2.0 contents revised

TMPM372FWUG *************************************************************************************************************** arm, arm powered, amba, adk, arm9tdmi, tdmi, primecell, realview, thumb, cortex, coresight, arm9, arm926ej-s, embedded trace macrocell, etm, ahb, apb, and keil are registered trademarks or trademarks of arm limited in the eu and other countries. **************************************************************************************************************** ?
y TMPM372FWUG
page 1-1 TMPM372FWUG 2013/4/15 TMPM372FWUG TMPM372FWUG is a 32-bit risc microprocessor series with an arm cortex ? -m3 microprocessor core. features of the TMPM372FWUG are as follows: 1.1 features 1. arm cortex-m3 microprocessor core a. improved code efficiency has been realized through the use of thumb ? -2 instruction. ? new 16-bit thumb instructions for improved program flow ? new 32-bit thumb instructions for improved performance ? new thumb mixed 16-/32-bit instruction set can produce faster, more efficient code. b. both high performance and low power consumption have been achieved. [high performance] ? 32-bit multiplication (32 32 = 32bit) can be executed with one clock. ? division takes between 2 and 12 cycles depending on dividend and devisor [low power consumption] ? optimized design using a low power consumption library ? standby function that stops the operation of the micro controller core c. high-speed interrupt response suitable for real-time control ? an interruptible long instruction. ? stack push automatically handled by hardware. 2. on chip program memory and data memory ? on-chip ram : 6kbyte ? on-chip flashrom : 128kbyte 3. 16-bit timer (tmrb) : 8 channels ? 16-bit interval timer mode ? 16-bit event counter mode ? input capture function ? external trigger ppg output 4. watchdog timer (wdt) : 1 channel watchdog timer (wdt) generates a reset or a non-maskable interrupt (nmi). product name rom (flash) ram package TMPM372FWUG 128 kbyte 6 kbyte p-lqfp64-1010-0.50e
page 1-2 1.1 features TMPM372FWUG 2013/4/15 5. power_on reset function (por) 6. voltage detect function (vltd) 7. oscillation frequency detect function (ofd) 8. vector engine (ve) : 1unit ? calculation circuit for motor control 9. programmable motor driver (pmd) : 1channels ? 3phase complementary pwm generator ? synchronous ad convert start trigger generator ? emergency protective function (emg ) 10. encoder input circuit (enc) : 1channels ? correspond to incremental encoder (ab / abz) ? rotation direction detection ? counter for absolute position detection ? comparator for position detection ? noise filter ? 3 phase sensor input 11. general-purpose serial interface(sio/uart) : 4channels either uart mode or synchronous mode can be selected (4byte fifo equipped) 12. 12 bit ad converter (adc) : 1units ( analog input : 11channel ) ? start by the internal trigger : tmrb interrupt / pmd trigger ? constant conversion mode ? ad monitoring 2ch ? conversion speed 2 sec (@adc conversion clock = 40 mhz) 13. input/ output ports (port) : 53 pins i/o pin : 53 pins 14. interrupt source ? internal 49 factors : the order of precedence can be set over 7 levels . (except the watc hdog timer inter- rupt) ? external 10 factors : the order of precedence can be set over 7 levels. 15. standby mode standby modes : idle, stop 16. clock generator (cg) ? on-chip pll (8 times) ? clock gear function : the high-speed clock can be divided into 1/1, 1/2, 1/4, 1/8 or 1/16.
page 1-3 TMPM372FWUG 2013/4/15 17. endian little endian 18. internal high-speed oscillation circuit 19. maximum operating frequency : 80 mhz 20. operating voltage range 4.5 v to 5.5 v ( with on-chip regulator ) 21. temperature range ? ?40 c to 85 c (except during flash writing / 1 to 80 mhz) ? ?40 c to 105 c (except during flash writing / 1 to 32 mhz) ?0 c to 70 c (during flash writing / erasing) 22. package ? p-lqfp64-1010-0.50e (10 mm 10 mm, 0.5 mm pitch)
page 1-4 1.2 block diagram TMPM372FWUG 2013/4/15 1.2 block diagram figure 1-1 tmpm372f wug block diagram i-code ahb-bus-matrix (80mhz) d-code system cortex-m3 cpu debug nvic bus bridge i/f nano flash i/f ram i/f boot rom regulator 3.3v 1.5v 5v cg pll wdt ofd on_chip oscillator por/vlvd sio tmrb port a - m ve pmd adc enc ve !a rom io-bus oscillator internal high-speed oscillator
page 1-5 TMPM372FWUG 2013/4/15 1.3 pin layout (top view) the pin layout of TMPM372FWUG is a figure below. figure 1-2 pin layout (lqfp64) 2'6$176 2'6$176 2(6$176 2('0%<4:& 2('0%$6:& 2('0%#5%.-%65 2'6$+0+06 2'5%.-%65 2'4:& 2'6:& 2$6/559&+1 2$6%-59%.- 2$6&1598 2$6&+ 2$6456 2$64#%'&#6# 2,#+0$ 2,#+0$ 2,#+0$ 2+#+0$ 4'5'6 8176 48&& /1&' 8176 2/: &855 2/: &8&& 2#+066$+0 2#6$176 2#+066$+0 #+0$2, #+0$2, #+0$2, +06%#+0$2, +06&#+0$2, +06'#+0$2- +06(#+0$2- 84'(.$#855$ 84'(*$#8&&$ +066$1762' +066$+02' 4:&6$+02# 6:&6$1762# 5%.-%652# +066$+02# 6$1762# 5%.-%652& 6:&2& 4:&2& 712) :12) 812) ;12) 912) <12) '/)2) 1882) &855 &8&& $1166$+02( 64#%'%.-2$ 64#%'&#6#2$ TMPM372FWUG
page 1-6 1.4 pin names and functions TMPM372FWUG 2013/4/15 1.4 pin names and functions table 1-1 sorts the input and output pins of the tmpm372f wug by pin or port. each table includes alternate pin names and functions for multi-function pins. 1.4.1 sorted by port table 1-1 pin names and functions sorted by port (1/4) port type pin no. pin name input / output function port a function 33 pa0 tb0in int3 i/o i i i/o port inputting the timer b capture trigger external interrupt pin port a function 34 pa1 tb0out i/o o i/o port timer b output port a function 35 pa2 tb1in int4 i/o i i i/o port inputting the timer b capture trigger external interrupt pin port a function 64 pa3 tb1out i/o o i/o port timer b output port a function 62 pa4 sclk1 cts1 i/o i/o i i/o port serial clock input/ output handshake input pin port a function 61 pa5 txd1 tb6out i/o o o i/o port sending serial data timer b output port a function 60 pa6 rxd1 tb6in i/o i i i/o port receiving serial data inputting the timer b capture trigger port a function 63 pa7 tb4in int8 i/o i i i/o port inputting the timer b capture trigger external interrupt pin port b function/ debug 15 pb0 traceclk i/o o i/o port debug pin port b function/ debug 16 pb1 tracedata0 i/o o i/o port debug pin port b function/ debug 17 pb2 tracedata1 i/o o i/o port debug pin port b function/ debug 22 pb3 tms/swdio i/o i/o i/o port debug pin port b function/ debug 21 pb4 tck/swclk i/o i i/o port debug pin port b function/ debug 20 pb5 tdo/swv i/o o i/o port debug pin port b function/ debug 19 pb6 tdi i/o i i/o port debug pin port b function/ debug 18 pb7 trst i/o i i/o port debug pin port d function 1 pd4 sclk2 cts2 i/o i/o i i/o port serial clock input/ output handshake input pin
page 1-7 TMPM372FWUG 2013/4/15 port d function 2 pd5 txd2 i/o o i/o port sending serial data port d function 3 pd6 rxd2 i/o i i/o port receiving serial data port e function 23 pe0 txd0 i/o o i/o port sending serial data port e function 24 pe1 rxd0 i/o i i/o port receiving serial data port e function 25 pe2 sclk0 cts0 i/o i/o i i/o port serial clock input/ output handshake input pin port e function 32 pe3 tb4out i/o o i/o port timer b output port e function 26 pe4 tb2in int5 i/o i i i/o port inputting the timer b capture trigger external interrupt pin port e function 31 pe5 tb2out i/o o i/o port timer b output port e function 59 pe6 tb3in int6 i/o i i i/o port inputting the timer b capture trigger external interrupt pin porte function 58 pe7 tb3out int7 i/o o i i/o port timer b output external interrupt pin port f function/ control 14 pf0 tb7in boot i/o i i i/o port inputting the timer b capture trigger boot mode pin. (note) this pin goes into single boot mode by sampling "low" at the rise of a reset signal. port f function 30 pf1 tb7out i/o o i/o port timer b output port f function 27 pf2 enca1 sclk3 cts3 i/o i i/o i i/o port encoder input serial clock input/ output handshake input pin port f function 28 pf3 encb1 txd3 i/o i o i/o port encoder input sending serial data port f function 29 pf4 encz1 rxd3 i/o i i i/o port encoder input receiving serial data port g function 4 pg0 uo1 i/o o i/o port u-phase output pin port g function 5 pg1 xo1 i/o o i/o port x-phase output pin port g function 6 pg2 vo1 i/o o i/o port v-phase output pin port g function 7 pg3 yo1 i/o o i/o port y-phase output pin table 1-1 pin names and functions sorted by port (2/4) port type pin no. pin name input / output function
page 1-8 1.4 pin names and functions TMPM372FWUG 2013/4/15 port g function 8 pg4 wo1 i/o o i/o port w-phase output pin port g function 9 pg5 zo1 i/o o i/o port z-phase output pin port g function 10 pg6 emg1 i/o i i/o port emergency status detection input port g function 11 pg7 ovv1 i/o i i/o port overvoltage detection input port i function 45 pi3 ainb2 i/o i i/o port analog input port j function 46 pj0 ainb3 i/o i i/o port analog input port j function 47 pj1 ainb4 i/o i i/o port analog input port j function 48 pj2 ainb5 i/o i i/o port analog input port j function 49 pj3 ainb6 i/o i i/o port analog input port j function 50 pj4 ainb7 i/o i i/o port analog input port j function 51 pj5 ainb8 i/o i i/o port analog input port j function 52 pj6 intc ainb9 i/o i i i/o port external interrupt pin analog input port j function 53 pj7 intd ainb10 i/o i i i/o port external interrupt pin analog input port k function 54 pk0 inte ainb11 i/o i i i/o port external interrupt pin analog input port k function 55 pk1 intf ainb12 i/o i i i/o port external interrupt pin analog input port m function / clock 37 pm0 x1 i/o i i/o port co nnected to a high-speed oscillator port m function / clock 39 pm1 x2 i/o o i/o port connected to a high-speed oscillator - control 41 mode i mode pin (note) mode pin must be connected to gnd. -function44 reset i reset input pin (note) with a pull-up and a noise filter (about 30ns (typical value)) -p s1 2d v s s ? gnd pin -p s3 8d v s s ? gnd pin -p s1 3d v d d 5 ? power supply pin -p s3 6d v d d 5 ? power supply pin table 1-1 pin names and functions sorted by port (3/4) port type pin no. pin name input / output function
page 1-9 TMPM372FWUG 2013/4/15 note 1: avss must be connected to gnd even if the ad converter is not used. note 2: must be connected to power suppl y even if ad converter is not used. - ps 42 rvdd5 ? power supply pin -p s4 0v o u t 1 5 ? power supply pin -p s4 3v o u t 3 ? power supply pin -p s5 6 avssb vreflb ? ad converter: gnd pin (note 1) supplying the ad converter with a reference power supply. -p s5 7 avdd5b vrefhb ? supplying the ad converter with a power supply. (note2) supplying the ad converter with a reference power supply. table 1-1 pin names and functions sorted by port (4/4) port type pin no. pin name input / output function
page 1-10 1.5 pin numbers and power supply pins TMPM372FWUG 2013/4/15 1.5 pin numbers and power supply pins note: vout15 and vout3 must be connected with the same value of capacitors. table 1-2 pin numbers and power supplies power supply voltage range pin no. pin name dvdd5 4.5 to 5.5v 13 , 36, pa,pb,pc,pd,pe,pf,pg,pl,pm pn, reset ,mode avdd5b 57 pj rvdd5 42 ? vout15 1.35 to 1.65v 40 vout15 must be connected to dvss through 3.3 to 4.7 f capacitor for supply power to internal circuit. vout3 2.7 to 3.6v 43 vout3 must be connected to dvss through 3.3 to 4.7 f capacitor for supply power to internal circuit.
page 2-1 TMPM372FWUG 2013/4/15 2. processor core the tx03 series has a high-performance 32-bit processor core (the arm cortex-m3 processor core). for infor- mation on the operations of this processor core, please re fer to the "cortex-m3 technical reference manual" issued by arm limited.this chapter describes the functions unique to the tx03 series that are not explained in that docu- ment. 2.1 information on the processor core the following table shows the revision of the processor core in the TMPM372FWUG. refer to the detailed information about the cpu core an d architecture, refer to the arm manual "cortex-m series processors" in th e following url: http://infocenter.arm.com/help/index.jsp 2.2 configurable options the cortex-m3 core has optional blocks. the optional blocks of the revision r2p0 are etm ? and mpu. the fol- lowing tables shows the configurable options in the TMPM372FWUG. product name core revision TMPM372FWUG r2p0 configurable options implementation fpb two literal comparators six instruction comparators dwt four comparators itm implementable mpu not implementable etm implementable ahb-ap implementable ahb trace macrocell interface implementable tpiu implementable wic not implementable
page 2-2 2. processor core 2.3 exceptions/ interruptions TMPM372FWUG 2013/4/15 2.3 exceptions/ interruptions exceptions and interruptions are described in the following section. 2.3.1 number of interrupt inputs the number of interrupt inputs can optionally be defined from 1 to 240 in the cortex-m3 core. TMPM372FWUG has 59 interrupt inputs. the number of interrupt inputs is reflected in bit of nvic register. in this product, if read bit, 0x00 is read out. 2.3.2 number of priori ty level interrupt bits the cortex-m3 core can optionally configure the number of priority level interrupt bits from 3 bits to 8 bits. TMPM372FWUG has 3 priority level interrupt bits. the nu mber of priority level interrupt bits is used for assigning a priority level in the interrupt priority registers and system handler priority registers. 2.3.3 systick the cortex-m3 core has a systick timer which can generate systick exception. for the detail of systick exception, refer to the sec tion of "systick" in the exception and the register of systick in the nvic register. 2.3.4 sysresetreq the cortex-m3 core outputs sysresetreq signal when bit of application interrupt and reset control register are set. TMPM372FWUG provides the same operation when sysresetreq signal are output. 2.3.5 lockup when irreparable exception generates, the cortex-m3 core out puts lockup signal to show a serious error included in software. TMPM372FWUG does not use this signal. to return from lockup status, it is necessary to use non- maskable interruput (nmi) or reset. 2.3.6 auxiliary fault status register the cortex-m3 core provides auxiliary fault status registers to supply additional system fault information to software. however, TMPM372FWUG is not defined this function. if auxiliary fault status register is read, always "0x0000_0000" is read out.
page 2-3 TMPM372FWUG 2013/4/15 2.4 events the cortex-m3 core has event output signals and event input signals. an event output signal is output by sev instruction execution. if an event is input, the core returns from low-power consumption mode caused by wfe instruction. TMPM372FWUG does not use event output signals and even t input signals. please do not use sev instruction and wfe instruction. 2.5 power management the cortex-m3 core provides power management syst em which uses sleeping signal and sleepdeep signal. sleepdeep signals are output when bit of system control register is set. these signals are output in the following circumstances: -wait-for-interrupt (wfi) instruction execution -wait-for-event (wfe) instruction execution -the timing when interrupt-service-routine (isr) exit in case that bit of system control regis- ter is set. TMPM372FWUG does not use sleepdeep signal so that bit must not be set. and also event signal is not used so that please do not use wfe instruction. for detail of power management, refer to the chapter "clock/mode control." 2.6 exclusive access in cortex-m3 core, the dcode bus system supports exclusive access. however TMPM372FWUG does not use this function.
page 2-4 2. processor core 2.6 exclusive access TMPM372FWUG 2013/4/15
page 3-1 mpm372fwug 2013/4/15 3. memory map 3.1 memory map the memory maps for mpm372fwug are based on the arm cortex-m3 processor core memory map. the inter- nal rom, internal ram and special function register s (sfr) of mpm372fwug are mapped to the code, sram and peripheral regions of the cortex-m3 respectively. the sp ecial function register (sfr) means the control registers of all input/output ports and peripheral functions. the sram and sfr areas are all included in the bit-band region. the cpu register area is the processo r core?s internal register region. for more information on each region, see th e "cortex-m3 technical reference manual". note that access to regions indicated as "fault" causes a memory fault if memo ry faults are enabled, or causes a hard fault if memory faults are disabled. also, do not access the ve ndor-specific region. 3.1.1 mpm372fwug memory map figure 3-1 shows the memory map of the mpm372fwug. figure 3-1 memory map sfr +pvgtpcnram (6k) internal rom (128k) za z((a(((( za za za za vendor-specific cpu register region fault fault fault z'a z'(a(((( z'a z((((a(((( sfr fault za z((a( z((a'((( za(((( za
page 3-2 3. memory map 3.2 details of sfr area mpm372fwug 2013/4/15 3.2 details of sfr area table 3-1 shows the de tails of the sfr area. do not access a reserved area in table 3-1. see the chaper of each peripheral function for datails. table 3-1 details of sfr start address end address peripheral 0x4000_0000 0x4000_033f port 0x4000_0340 0x4000_ffff reserved 0x4001_0000 0x4001_01ff tmrb 0x4001_0200 0x4001_04ff reserved 0x4001_0500 0x4001_053f enc 0x4001_0540 0x4002_007f reserved 0x4002_0080 0x4002_017f sio/uart 0x4002_0180 0x4003_01f reserved 0x4003_0200 0x4003_02ff adc 0x4003_0300 0x4003_ffff reserved 0x4004_0000 0x4004_003f wdt 0x4004_0040 0x4004_01ff reserved 0x4004_0200 0x4004_023f cg 0x4004_0240 0x4004_02ff reserved 0x4004_0300 0x4004_030f trm 0x4004_0310 0x4004_07ff reserved 0x4004_0800 0x4004_083f ofd 0x4004_0840 0x4004_08ff reserved 0x4004_0900 0x4004_093f vltd 0x4004_0940 0x4004_ffff reserved 0x4005_0000 0x4005_01ff ve 0x4005_0200 0x4005_047f reserved 0x4005_0480 0x4005_04ff pmd 0x4005_0500 0x4007_ffff reserved 0x4008_0000 0x41ff_efff hard fault 0x41ff_f000 0x41ff_f03f flash 0x41ff_f040 0x41ff_ffff reserved
page 4-1 TMPM372FWUG 2013/4/15 4. reset operation 4.1 initial state the internal circuits, register settings and pin status are undefined right after the power-on. the state continues until the reset pin receives "low" level signal after all the power supply voltage is applied. 4.2 reset operation TMPM372FWUG has power-on reset circuit, power-on rese t signal is generated when power supply is turned on. when reset from external reset pin, input reset signa l to reset pin at "low" level for minimum duration of 1.2 sec while power supply voltage is in the operating range. 4.3 after reset when the reset is released, the system control register and the internal i/o register of the cortex-m3 processor core are initialized. note that the pll multiplication circ uit stops after releasing the reset. therefore, set cgosccr register and cgpllsel register to use pll multiplication circuit. after the reset exception handling is executed, the progra m branches off to the interrupt service routine. the address with which the interrupt service routine starts is stored in 0x0000_0004. note 1: it is possible to turn power on after reset pin is set to "low". note 2: the reset operation may alter the internal ram state.
page 4-2 4. reset operation 4.3 after reset TMPM372FWUG 2013/4/15
page 5-1 TMPM372FWUG 2013/4/15 5. clock / mode control 5.1 features the clock/mode control block enables to select clock gear, prescaler clock and warm-up of the pll clock multipli- cation circuit and oscillator. there is also the low power consumption mode which can reduce power consumption by mode transitions. this chapter describes how to control clock operating modes and mode transitions. the clock/mode control block has the following functions: ? controls the system clock ? controls the prescaler clock ? controls the pll multiplication circuit ? controls the warm-up timer in addition to normal mode, the TMPM372FWUG can operate in six types of low power mode to reduce power consumption according to its usage conditions.
page 5-2 5. clock / mode control 5.2 registers TMPM372FWUG 2013/4/15 5.2 registers 5.2.1 register list the following table shows the cg-r elated register s and addresses. base address = 0x4004_0200 register name address (base+) system control register cgsyscr 0x0000 oscillation control register cgosccr 0x0004 standby control register cgstbycr 0x0008 pll selection register cgpllsel 0x000c system clock select register cgcksel 0x0010
page 5-3 TMPM372FWUG 2013/4/15 5.2.2 cgsyscr (system control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000001 15 14 13 12 11 10 9 8 bit symbol - - - fpsel - prck after reset00000000 7 6 5 4 3 2 1 0 bit symbol----- gear after reset00000000 bit bit symbol type function 31-18 ? r read as "0". 17-16 ? r/w write as "01". 15-13 ? r read as "0". 12 fpsel r/w selects fperiph source clock 0: fgear 1: fc 11 ? r read as "0". 10- 8 prck[2:0] r/w prescaler clock 000: fperiph 001: fperiph/2 010: fperiph/4 011: fperiph/8 100: fperiph/16 101: fperiph/32 110: reserved 111: reserved specifies the prescaler clock to peripheral i/o. 7-3 ? r read as "0". 2-0 gear[2:0] r/w high-speed clock (fc) gear 000: fc 001: reserved 010: reserved 011: reserved 100: fc/2 101: fc/4 110: fc/8 111: fc/16
page 5-4 5. clock / mode control 5.2 registers TMPM372FWUG 2013/4/15 5.2.3 cgosccr (oscilla tion control register) 31 30 29 28 27 26 25 24 bit symbol wuodr after reset10000000 23 22 21 20 19 18 17 16 bit symbol wuodr wupsel2 hoscon oscsel xen2 after reset00000001 15 14 13 12 11 10 9 8 bit symbol-------xen1 after reset00000000 7 6 5 4 3 2 1 0 bit symbol----wupsel1pllonwuefwueon after reset00000000
page 5-5 TMPM372FWUG 2013/4/15 note 1: when the is set to "1", the all register s for port m can not be accessed and the read data from these registers are always "0". if one of the port m registers except pmdata and pmod is not equal to the initial value, the can not be set to "1". note 2: do not write "1" to , at the setting of returning from stop mode with automatic warming-up. when warming-up is started by software ( = "1" ), please monitor and confirm warming-up is completed. after turn to "0" operation mode can be changed to stop mode. bit bit symbol type function 31-20 wuodr[11:0] r/w specifies count time of the warm-up timer. 19 wupsel2 r/w clock source for warm-up timer(wup) 0: internal (osc2) 1: external (osc1) select source clock for warm-up timer between external oscillator (osc1) and internal oscillator (osc2). 18 hoscon r/w port m or external oscillator (x1/x2) (note1) 0: port m 1: external oscillator (x1/x2) specifies port m or x1/x2. when the external oscillator (osc1) is used, port m registers (pmcr/pmpup/pmpdn/pmie) should be dis- abled. after reset, the port m registers are disabled. 17 oscsel r/w selection of high-speed oscillator 0: internal (osc2) 1: external (osc1) select high-speed oscillator between external oscillato r (osc1) and internal oscillator (osc2). confirm become "1" then halt the osc2 immediately after switching over to osc1. do not select osc2 again after switching to osc1. 16 xen2 r/w high-speed oscillator2 (internal) 0: stop 1:oscillation specifies operation of the high-speed oscillator 2 (osc2). 15-12 ? r/w write as "0". 11-10 ? r read as "0". 9 ? r/w write as "0". 8 xen1 r/w high-speed oscillator1 (external) 0: stop 1:oscillation specifies operation of the high-speed oscillator 1 (osc1). 7-4 ? r/w read as "0". 3 wupsel1 r/w clock source for warm-up timer write as "0". 2 pllon r/w pll operation 0: stop 1: oscillation specifies operation of the pll. it stops after reset.setting the bit is required. 1 wuef r status of warm-up timer (wup) (note2) 0: warm-up completed. 1: warm-up operation enable to monitor the status of the warm-up timer. 0 wueon w operation of warm-up timer (note2) 0: don't care 1: starting warm-up enables to start the warm-up timer.
page 5-6 5. clock / mode control 5.2 registers TMPM372FWUG 2013/4/15 5.2.4 cgstbycr (standby control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------drve after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------rxen after reset00000001 7 6 5 4 3 2 1 0 bit symbol----- stby after reset00000011 bit bit symbol type function 31-18 ? r read as "0". 17 ? r/w write as "0". 16 drve r/w pin status in stop mode 0: inactive 1: active 15-10 ? r read as "0". 9 ? r/w write as "0". 8 rxen r/w high-speed oscillator operation after releasing the stop mode. write as "1". 7-3 ? r read as "0". 2-0 stby[2:0] r/w low power consumption mode 000: reserved 001: stop 010: reserved 011: idle 100: reserved 101: reserved 110: reserved 111: reserved to enter the stop mode, disable the oscillation (osc1 or osc2) which is unused as system clock.
page 5-7 TMPM372FWUG 2013/4/15 5.2.5 cgpllsel (pll selection register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset10100001 7 6 5 4 3 2 1 0 bit symbol-------pllsel after reset00111110 bit bit symbol type function 31-16 ? r read as "0". 15-12 ? r/w write as "1010". 11 ? r read as "0". 10-1 ? r/w write as "00_1001_1111". 0 pllsel r/w use of pll 0: fosc use 1: pll use specifies use or disuse of the clock multiplied by the pll. "fosc" is automatically set after reset. resetting is required when using the pll.
page 5-8 5. clock / mode control 5.3 clock control TMPM372FWUG 2013/4/15 5.3 clock control 5.3.1 clock type each clock is defined as follows : the high-speed clock fc and the prescaler clock t0 are dividable as follows. 5.3.2 initial values after reset reset operation initializes the clock configuration as follows. reset operation causes all the clock co nfigurations to be the same as f osc2 . fosc1 : clock input from external high-speed oscillator (x1 and x2) fosc2 : clock input from internal high-speed oscillator fosc : high-speed clock specified by cgosccr f pll : clock octupled by pll fc : clock specified by cgpllsel (high-speed clock) fgear : clock specifi ed by cgsyscr fsys : the same clock as fgear (system clock) fperiph : clock specif ied by cgsyscr t0 : clock specified by cgsyscr (prescaler clock) high-speed clock : fc, fc/2, fc/4, fc/8, fc/16 prescaler clock : fperiph, fperiph/2, fperiph/4, fperiph/8, fperiph/16, fperiph/32 high-speed oscillator 1 (external) : stop high-speed oscillator 2 (internal) : oscillating pll (phase locked loop circuit) : stop high-speed clock gear : fc (no frequency dividing) f c = f osc2 f sys = f c ( = f osc2 ) f periph = f c ( = f osc2 ) t0 = f periph ( = f osc2 )
page 5-9 TMPM372FWUG 2013/4/15 5.3.3 clock system diagram figure 5-1 shows the clock system diagram. figure 5-1 clock block diagram the input clocks selector shown with an arrow are set as default after reset. warm-up timer cgosccr cgosccr internal oscillator pll ad conversion clock ofd monitoring clock cgsyscr fgear fperiph (to peripheral i/o) fsys cgpllsel cgosccr external oscillator cgosccr starts oscillation after reset fosc2 cgosccr stops after releasing reset cgosccr stops oscillation after reset f pll = f osc 8 fc cgsyscr peripheral i/o prescaler input 1/32 1/16 1/8 cgsyscr 1/4 1/2 fperiph tt0 systick external refference clock cpu ahb-bus i/o cpu, rom, ram, boot rom io-bus i/o tmrb, wdt, ve, pmd, sio, adc, port, ofd, enc, vltd fosc1 fosc 1/8 1/4 1/2 1/16 cgosccr 1/32 x2 x1 tmrb, sio
page 5-10 5. clock / mode control 5.3 clock control TMPM372FWUG 2013/4/15 5.3.4 clock multiplication circuit (pll) this circuit outputs the f pll clock that is octuple of the high-speed oscillator output clock (fosc.) as a result, the input frequency to oscillator can be low, and the internal clock be made high-speed. the pll is disabled after reset. to enable the pll, set "1" to the cgosccr bit and set "1" to the cgpllsel. then f pll clock output is octuple of the high-speed oscillator (fosc). the pll requires a certain amount of time to be st abilized, which should be secured using the warm-up functionor other methods. note:it takes approximately 200 s for the pll to be stabilized. 5.3.4.1 the sequence of pll setting the following shows pll setting sequence after reset. figure 5-2 pll sett ing sequence after reset note: when you stop pll, please check that it is the register cgpllsel = "0" after setting up the cgpllsel = "0". then, please set up cgosccr = "0" (pll stoped). initial value after reset cgosccr= 0 (pll stopped) cgpllsel= 0 (fosc selected) cgsyscr= 1/1 (clock gear) need stable high-speed oscillation and power supply voltage. operation flow notes it is possible to use the clock mulitpied . enable pll operation cgosccr= 1 (pll active) pll operation selected cgpllsel= 1 (pll input) it takes approximately 200s for the pll to be stabilized.
page 5-11 TMPM372FWUG 2013/4/15 5.3.5 warm-up function the warm-up function secures the stability time for the oscillator and the pll with the warm-up timer. the warm-up function is used when returning from stop mo de. for detail function, describes in "5.6.6 warm-up". note:do not shift to stop mode, during operating warm-up timer. in this case, an interrupt for returning from the lo w power consumption mode triggers the automatic timer count. after the specified time is reached, the syst em clock is output and the cpu starts operation. in stop modes, the pll is disabled. when returning from these modes, configur e the warm-up time in con- sideration of the stability time of the pll and the internal oscillator. how to configure the warm-up function. 1. specify the count up clock specify the count up clock for the warm -up counter in the cgosccr and bit. ( write "0" to and write "0" or "1 " to . "0" specifies internal oscillator and "1" sp ecifies external oscillator.) 2. specify the warm-up counter value the warm-up time can be selected by setting the cgosccr. the following shows the wa rm-up setting and example. setting 5 ms of warm-up time with 8mhz oscillator drop the last 4 bits, set 0x9c4 into the cgosccr. 3. confirm the start and completion of warm-up the cgosccr is used to conf irm the start and co mpletion of warm-up through software (instruction). note: the warm-up timer operates according to the oscillation clock, and it may contain errors if there is any fluctuation in th e oscillation frequency. therefore, the warm- up time should be taken as approximate time. warm-up cycles = setting value of warm-up time input cycle by frequency(s) setting value of warm-up time input cycle by frequency(s) = 5ms 1/8mhz = 40,000f\fohv 0x9c40
page 5-12 5. clock / mode control 5.3 clock control TMPM372FWUG 2013/4/15 the following shows the warm-up setting. securing the stability time for the pll (fc = fosc1) cgosccr = "0" : write "0" to cgosccr cgosccr = "1" : specify the clock source for warm-up timer cgosccr = "0x9 c4" : warm-up time setting refer to 5.3.6 for the procedure of switching over from the internal oscillator to the external oscillator. cgosccr="1" : enable warm-up counting (wup) read cgosccr : wait until the st ate becomes "0" (warm-up is finished)
page 5-13 TMPM372FWUG 2013/4/15 5.3.6 system clock the TMPM372FWUG offers high-speed clock as system clock. system clock is selectable from internal oscillator or external oscillator. after reset, internal oscillator is enabled and external oscillator is disabled. the high-speed clock is dividable. ? input frequency from x1 and x2 : 8 mhz to 10mhz ? internal oscillator frequency : 10mhz ? clock gear : 1/1, 1/2, 1/4, 1/8, 1/16 (after reset : 1/1) note 1: pll=on/off setting: available in cgosccr. note 2: switching of clock gear is executed when a value is written to the cgsyscr register. the actual switching takes place after a slight delay. note 3: ."-" : reserved note 4: do not use 1/16 when "pll =off" is used. note 5: do not use 1/16 when systick is used. note 6: the maximum operating frequency is 32 mhz when using within the range from 85 to 105 c. be careful not to exceed the maximum operating frequency by dividing system clock when using pll. the following are the procedure of switching over from the internal oscillator to the external oscillator. with setting cgosccr to "1", rewrit ing the portm registers (pmdata/pmcr/pmod/ pmpup/pmpdn/pmie) are prohibited. table 5-1 range of high-speed frequency (unit : mhz) input freq. min. oper- ating freq. max. oper- ating freq. after reset (pll = off, cg = 1/1) clock gear (cg) : pll = on clock gear (cg) : pll = off 1/1 1/2 1/4 1/8 1/16 1/1 1/2 1/4 1/8 1/16 osc1 8 1 80 8 643216848421 - 10 10 80 40 20 10 5 10 5 2.5 1.25 - osc2 10 10 80 40 20 10 5 10 5 2.5 1.25 - 1. disables port m registers (pmcr/pmpup/pmpdn/pmie). after reset, these registers are disabled. 2. cgosccr = "warm-up time" : set warm-up time. 3. cgosccr = "1" : switch over from the port m to oscillator connection pins.. 4. cgosccr = "1" : enable the external oscillator. 5. cgosccr = "1" : specify the external oscillato r clock as source clock for warm-up counter. 6. cgosccr="1" : enable warm-up counting (wup) read cgosccr : wait until the state becomes "0" (warm-up is finished) 7. cgosccr = "1" : switch the system clock to the external oscillator. 8. read cgosccr : confirm cgosccr[17] become "1". (external oscillator is selected.) 9. cgosccr = "0" : internal oscillator is disabled.
page 5-14 5. clock / mode control 5.3 clock control TMPM372FWUG 2013/4/15 5.3.7 prescaler clock control each peripheral function has a prescaler for dividing a clock. as the clock t0 to be input to each prescaler, the "fperiph" clock specified in the cgsyscr can be divided according to the setting in the cgsy- scr. after the controller is reset, fperiph/1 is selected as t0. note:to use the clock gear, ensure that you make the time setting such that prescaler output tn from each periph- eral function is sl ower than fsys ( tn < fsys). do not switch the clock gear while the timer counter or other peripheral function is operating.
page 5-15 TMPM372FWUG 2013/4/15 5.4 modes and mode transitions 5.4.1 mode transitions the normal mode use the high-speed clock for the system clock . the idle and stop modes can be used as the low power consumption mode that enables to reduce power consumption by halting processor core operation. figure 5-3 shows mode transition diagram. for a detail of sleep-on-exit, refer to "cortex-m3 technical reference manual". figure 5-3 mode transition diagram note:the warm-up is needed. the warm-up time must be set in normal mode before changing to stop mode. regarding warm-up time, refer to "5.6.6 warm-up". reset has been performed. interrupt (note) normal mode reset idle mode (stops cpu) (selectable io operation) stop mode (halts all circuit) instruction/ sleep on exit instruction/ sleep on exit interrupt (note)
page 5-16 5. clock / mode control 5.5 operation mode TMPM372FWUG 2013/4/15 5.5 operation mode as an operation mode, normal is av ailable. the features of normal mode are described in the following sec- tion. 5.5.1 normal mode this mode is to operate the cpu core and the pe ripheral hardware by using the high-speed clock. it is shifted to the normal mode after reset.
page 5-17 TMPM372FWUG 2013/4/15 5.6 low power consumption modes the TMPM372FWUG has two low power consumption modes: idle and stop. to shift to the low power con- sumption mode, specify the mode in the system control register cgstby cr and execute the wfi (wait for interrupt) instruction.in this case, execute reset or generate the in terrupt to release the mode. releasing by the interrupt requires settings in advance. see the chapter "exceptions" for details. note 1: the TMPM372FWUG does not offer any event for releas ing the low power consumption mode. transition to the low power consumption mode by executing the wfe (wait for event) instruction is prohibited. note 2: the TMPM372FWUG does not support the low power consumption mode configured with the sleepdeep bit in the cortex-m3 core. setting the bit of the system control register is prohibited. the features of each mode are described as follows. 5.6.1 idle mode only the cpu is stopped in this mode. each peripheral function has one bit in its control register for enabling or disabling operation in the idle mode. when the idle mode is entered, peripheral functions for which operation in the idle mode is disabled stop operation and hold the state at that time. the following peripheral functions can be enabled or disabled in the idle mode. for setting details, see the chapter on each peripheral function. ? 16-bit timer / event counter (tmrb) ? serial channel (sio/uart) ? watchdog timer (wdt) ? vector engine (ve) note:wdt should be stopped before entering idle mode.
page 5-18 5. clock / mode control 5.6 low power consumption modes TMPM372FWUG 2013/4/15 5.6.2 stop mode all the internal circuits including the internal os cillator are brought to a stop in the stop mode. by releasing the stop mode, the de vice returns to the preceding mode of the stop mode and starts opera- tion. the stop mode enables to select the pin status by setting the cgstbycr. table 5-2 shows the pin status in the stop mode. table 5-2 pin states in the stop mode pin name i/o = 0 = 1 not port reset , mode input only x1 input only x2 output only "high" level output tms tck tdi trst input tdo output enabled when data is valid. disabled when data is invalid. swclk input swdio input output enabled when data is valid. disabled when data is invalid. port traceclk tracedata0 tracedata1 swv output uo0 vo0 wo0 xo0 yo0 zo0 output enabled when data is valid. disabled when data is invalid. int3, int4, int5 int6, int7 intc, intd, inte intf input other function pins other than the above or the ports that are used as general purpose ports. input output : input or output enabled. : input or output disabled.
page 5-19 TMPM372FWUG 2013/4/15 5.6.3 low power cons umption mode setting the low power consumption mode is specified by the setting of the standby control register cgst- bycr. table 5-3 shows the mode setting in the . note:do not set any value other than those shown above in . table 5-3 low power consumption mode setting mode cgstbycr stop 001 idle 011
page 5-20 5. clock / mode control 5.6 low power consumption modes TMPM372FWUG 2013/4/15 5.6.4 operational status in each mode table 5-4 shows the operational status in each mode. for i/o port, " " and " " indicate that input/output is enabled and disabled respectively. for other functions, " " and " " indicate that clock is supplied and is not supplied respectively. note 1: it depends on cgstbycr. note 2: the blocks are not stopped even though the clock is halted. 5.6.5 releasing the low power consumption mode the low power consumption mode can be released by an interrupt request, non-maskable interrupt (nmi) or reset. the release source that can be used is dete rmined by the low power consumption mode selected. details are shown in table 5-5. table 5-4 operational status in each mode block normal idle stop processor core ? i/o port ? * (note1) pmd ?? enc ?? ofd ?? adc ?? ve on/off selectable for each module sio ? sbi ? tmrb ? wdt ? vltd ?? (note2) por ?? (note2) cg ?? pll ?? high-speed oscilla- tor (fc) ?? : operating : stopped
page 5-21 TMPM372FWUG 2013/4/15 note 1: to release the low power consumption mode by usi ng the level mode interrupt, keep the level until the inter- rupt handling is started. changing the level before then will prevent the interrupt handling from starting properly. note 2: for shifting to the low power consumption mode, set the cpu to prohibit all the interrupts other than the release source. if not, releasing may be executed by an unspecified for wake up. note 3: refer to "5.6.6 warm-up" about warm-up time. ? release by interrupt request to release the low power consumption mode by an interrupt, the cpu must be set in advance to detect the interrupt. in addition to the setting in the cpu, the clock generator must be set to detect the interrupt to be used to release the stop modes. ? release by non-maskab le interrupt (nmi) there is a watchdog timer interr upt (intwdt) as a non-maskabl e interrupt source. intwdt can only be used in the idle mode. ? release by reset any low power consumption mode can be released by reset from the reset pin. after that, the mode switches to the normal mode and all the regi sters are initialized as is the case with normal reset. ? release by systick interrupt table 5-5 release source in each mode low power consumption mode idle (programable) stop int3 to 8, intc to f (note1) ? intrx0 to 3, inttx0 to 3 ? intvcnb ? intemg1 ? intovv1 ? intadbpda, intadbpdb ? release source interrupt inttb00, 10, 20, 30, 40, 50, 60, 70 inttb01, 11, 21, 31, 41, 51, 61, 71 ? intpmd0, 1 ? intcap00, 10, 20, 30, 40, 50, 60, 70 intcap01, 11, 21, 31, 41, 51, 61, 71 ? intadbcpa, intadbcpb ? intadbsft ? intadbtmr ? intenc1 ? systick ? nmi (intwdt) ? reset ( reset pin) ? : : starts the interrupt handling after the mode is released. (the reset initializes the lsi) unavailable
page 5-22 5. clock / mode control 5.6 low power consumption modes TMPM372FWUG 2013/4/15 systick interrupt can only be used in idle mode. refer to "interrupts" for detail.
page 5-23 TMPM372FWUG 2013/4/15 5.6.6 warm-up mode transition may require the warm-up so that the internal oscillator prov ides stable oscillation. in the mode transition from stop to the normal, the warm-up counter is activated automatically. and then the system clock output is starte d after the elapse of configured warm -up time. it is necessary to set a oscillator to be used for warm-up in the cgos ccr (note1 ) and to set a warm-up time in the cgosccr befo re executing the in struction to ente r the stop mode. note 1: always set cgosccr to "0". note 2: in stop modes, the pll is disabled. when returning from these mode, configure the warm-up time in con- sideration of the stability time of the pll and the internal oscillator. it takes approximately 200 s for the pll to be stabilized. note 3: do not write "1" to cgosccr bit, at th e setting of returning from low consumption mode with automatic warming-up. table 5-6 shows whether the warm-up setting of each mode transition is required or not. table 5-6 warm-up setting in mode transition mode transition warm-up setting normal idle not required normal stop not required idle normal not required stop normal auto-warm-up
page 5-24 5. clock / mode control 5.6 low power consumption modes TMPM372FWUG 2013/4/15 5.6.7 clock operation in mode transition the clock operation in mode transition are described chapter 5.6.7.1 . 5.6.7.1 transition of operation modes : normal stop normal when returning to the normal mode from the stop mode, the warm-up is activated automatically. it is necessary to set the warm-up time before entering the stop mode. returning to the normal mode by reset does not induce the automatic warm-up. keep the reset sig- nal asserted until the oscillat or operation becomes stable. fsys (system clock) stop fosc normal normal mode warm-up system clock stops high-speed clock starts oscillating warm-up starts wfi execute/ sleep on exit release event occurs warm-up completes. system clock starts.
page 6-1 TMPM372FWUG 2013/4/15 6. exceptions this chapter describes features, types and handling of exceptions. exceptions have close relation to the cpu core. refer to "cortex-m3 tec hnical reference manual" if needed. 6.1 overview exceptions have close relation to the cpu core. refer to "cortex-m3 tec hnical reference manual" if needed. there are two types of exceptions: those that are generate d when some error condition occurs or when an instruc- tion to generate an exception is executed; and those that ar e generated by hardware, such as an interrupt request sig- nal from an external pin or peripheral function. all exceptions are handled by the nested vectored inte rrupt controller (nvic) in the cpu according to the respective priority levels. when an excep tion occurs, the cpu stores the current state to the stack and branches to the corresponding interrupt service routine (isr). upon completi on of the isr, the information stored to the stack is automatically restored. 6.1.1 exception types the following types of exceptions exist in the cortex-m3. for detailed descriptions on each exception, refer to "cortex- m3 technical reference manual". ? reset ? non-maskable interrupt (nmi) ? hard fault ? memory management ? bus fault ? usage fault ? svcall (supervisor call) ? debug monitor ? pendsv ?systick ? external interrupt
page 6-2 6. exceptions 6.1 overview TMPM372FWUG 2013/4/15 6.1.2 handling flowchart each step is described later in this chapter. the following shows how an exception/interrupt is handled. in the following descriptions, indicates hardware handling. indicates software handling. processing description see detection by cg/cpu the cg/cpu detects the exception request. section 6.1.2.1 handling by cpu the cpu handles the exception request. section 6.1.2.2 branch to isr the cpu branches to the corresponding interrupt service routine (isr). execution of isr necessary proce ssing is executed. section 6.1.2.4 return from exception the cpu branches to another isr or returns to the previous program. section 6.1.2.4
page 6-3 TMPM372FWUG 2013/4/15 6.1.2.1 exception request and detection (1) exception occurrence exception sources include instruction execution by the cpu, memory accesses, and interrupt requests from external interrupt pins or peripheral functions. an exception occurs when the cpu executes an in struction that causes an exception or when an error condition occurs dur ing instruction execution. an exception also occurs by an in struction fetch from the execute never (xn) region or an access violation to the fault region. an interrupt request is generated from an extern al interrupt pin or peripheral function.for inter- rupts that are used for releasing a standby mode, rele vant settings must be made in the clock genera- tor. for details, refer to "6.5 interrupts". (2) exception detection if multiple exceptions occur simultaneously, the cpu takes the exception with the highest priority. table 6-1 shows the priority of exceptions. "conf igurable" means that you can assign a priority level to that exception. memory management, bus fault and usage fault exceptions can be enabled or disabled. if a disabled exception occurs, it is handled as hard fault. note 1: this product does not contain the mpu. note 2: external interrupts have different sources and numbers in each product. for details, see"6.5.1.5 list of interrupt sources". table 6-1 exception types and priority no. exception type priority description 1 reset ? 3 (highest) reset pin, wdt, por, vltd, ofd or sysretreq 2 non-maskable interrupt ? 2 w d t 3 hard fault ? 1 fault that cannot activate because a higher-priority fault is being han- dled or it is disabled 4 memory management configurable exception from the memory pr otection unit (mpu) (note 1) instruction fetch from the execute never (xn) region 5 bus fault configurable access violation to the hard fault region of the memory map 6 usage fault configurable undefined instruction execution or other faults related to instruction execution 7~10 reserved ? 11 svcall configurable system service call with svc instruction 12 debug monitor configurable debug monitor when the cpu is not faulting 13 reserved ? 14 pendsv configurable pendable system service request 15 systick configurable notification from system timer 16~ external interrupt configurable external in terrupt pin or peripheral function (note2)
page 6-4 6. exceptions 6.1 overview TMPM372FWUG 2013/4/15 (3) priority setting ? priority level the external interrupt priority is set to the interrupt priority register and other exceptions are set to bit in the system handler priority register. the configuration can be changed, and the number of bits required for setting the priority varies from 3 bits to 8 bits dependin g on products. thus, the range of priority values you can specify is different depending on products. in the case of 8-bit configuratio n, the priority can be configured in the range from 0 to 255. the highest priority is "0". if multiple elements with the same priority exist, the smaller the number, the higher the priority becomes. note: bit is defined as a 3-bit configuration with this product. ? priority grouping the priority group can be split into groups. by setting the of the application interrupt and reset control register, can be divided into the pre-emption priority and the sub priority. a priority is compared with th e pre-emption priority. if the pr iority is the same as the pre- emption priority, then it is compared with the sub priority. if the sub priority is the same as the priority, the smaller the exception number, the higher the priority. the table 6-2 shows the priority group setting. the pre-emption priority and the sub prior- ity in the table are the number in the case that is defined as an 8-bit configuration. note: if the configuration of is less than 8 bits, the lower bit is "0". for the example, in the case of 3-bit configuration, the priority is set as and is "00000". table 6-2 priority grouping setting setting number of pre-emption priorities number of subpriorities pre-emption field subpriority field 000 [7:1] [0] 128 2 001 [7:2] [1:0] 64 4 010 [7:3] [2:0] 32 8 011 [7:4] [3:0] 16 16 100 [7:5] [4:0] 8 32 101 [7:6] [5:0] 4 64 110 [7] [6:0] 2 128 111 none [7:0] 1 256
page 6-5 TMPM372FWUG 2013/4/15 6.1.2.2 exception handling and branch to the interrupt service routine (pre-emption) when an exception occurs, the cpu suspends the currently executing pr ocess and branches to the inter- rupt service routine. this is called "pre-emption". (1) stacking when the cpu detects an exception, it pushes the contents of the followin g eight registers to the stack in the following order : ? program counter (pc) ? program status register (xpsr) ?r0 to r3 ?r12 ? link register (lr) the sp is decremented by eight words by the completion of the stack push.the following shows the state of the stack after the regi ster contents have been pushed. (2) fetching an isr the cpu enables instruction to fetch the interrupt processing with data store to the register. prepare a vector table containing the top addresses of isrs for each exception.after reset, the vec- tor table is located at address 0x0000_0000 in the code area.by setting the vector table offset reg- ister, you can place the vector table at any address in the code or sram space. the vector table should also contain the initial value of the main stack. (3) late-arriving if the cpu detects a higher pr iority exception before executing the isr for a previous exception, the cpu handles the higher pr iority exception first. this is called "late-arriving". a late-arriving exception causes the cpu to fetch a new vector address for branching to the corre- sponding isr, but the cpu does not newly push the register contents to the stack. old sp xpsr pc lr r12 r3 r2 r1 sp r0
page 6-6 6. exceptions 6.1 overview TMPM372FWUG 2013/4/15 (4) vector table the vector table is configured as shown below. you must always set the first four words (stack top address, reset isr a ddress, nmi isr address, and hard fault isr address). set isr addr esses for other exceptions if necessary. 6.1.2.3 executing an isr an isr performs necessary processing for the corresponding exception. isrs must be prepared by the user. an isr may need to include code fo r clearing the interrupt request so that the same interrupt will not occur again upon return to normal program execution. for details about interrupt handling, see "6.5 interrupts". if a higher priority exception o ccurs during isr executio n for the current excep tion, the cpu abandons the currently executing isr and serv ices the newly detected exception. offset exception contents setting 0x00 reset initial value of the main stack required 0x04 reset isr address required 0x08 non-maskable interrupt isr address required 0x0c hard fault isr address required 0x10 memory management isr address optional 0x14 bus fault isr address optional 0x18 usage fault isr address optional 0x1c to 0x28 reserved 0x2c svcall isr address optional 0x30 debug monitor isr address optional 0x34 reserved 0x38 pendsv isr address optional 0x3c systick isr address optional 0x40 external interrupt isr address optional
page 6-7 TMPM372FWUG 2013/4/15 6.1.2.4 exception exit (1) execution after re turning from an isr when returning from an isr, the cpu takes one of the following actions : ? tail-chaining if a pending exception exists an d there are no stacked excepti ons or the pending exception has higher priority than all stacked exceptions, the cpu returns to the isr of the pending exception. in this case, the cpu skips the pop of eight re gisters and push of ei ght registers when exit- ing one isr and entering another. this is called "tail-chaining". ? returning to the last stacked isr if there are no pending excepti ons or if the highest priority stacked exception is of higher priority than the highest priority pending excep tion, the cpu returns to the last stacked isr. ? returning to the previous program if there are no pending or st acked exceptions, the cpu retu rns to the previous program. (2) exception exit sequence when returning from an isr, the cpu performs the following operations : ? pop eight registers pops the eight registers (pc, xpsr, r0 to r3, r12 and lr) from the stack and adjust the sp. ? load current active interrupt number loads the current active interrupt number fr om the stacked xpsr. the cpu uses this to track which interrupt to return to. ? select sp if returning to an exception (handler mode), sp is sp_main. if returning to thread mode, sp can be sp_main or sp_process.
page 6-8 6. exceptions 6.2 reset exceptions TMPM372FWUG 2013/4/15 6.2 reset exceptions reset exceptions are generated from the following six sources. use the reset flag (cgrstflg) register of the clock generator to identify the source of a reset. ? external reset pin a reset exception occurs when an external reset pin changes from "low" to "high". ? reset exception by por please refer the chapter "por power on reset circuit" for detail. ? reset exception by vltd please refer the chapter "vltd voltage detection circuit" for detail. ? reset exception by ofd please refer the chapter "ofd oscilla tion frequency detector" for detail. ? reset exception by wdt the watchdog timer (wdt) has a reset generating feature. for details, see the chapter on the wdt. ? reset exception by sysresetreq a reset can be generated by setting the sysresetreq bit in the nvic's application interrupt and reset control register. 6.3 non-maskable interrupts (nmi) the watchdog timer (wdt) has a non-maskable interrupt ge nerating feature. for details, see the chapter on the wdt. use the nmi flag (cgnmiflg) register of the clock generator to identify the source of a non-maskable inter- rupt. 6.4 systick systick provides interrupt features using the cpu's system timer. when you set a value in the systick reload value register and enable the systick features in the systick control and status register, the counter loads with the value set in the reload value register and begins counting down.when the counter reaches "0", a systick exception occurs.you may be pending exceptions and use a flag to know when the timer reaches "0". the systick calibration value register holds a reload value for counting 10 ms with the system timer. the count clock frequency varies with each product, and so the value set in the sy stick calibration value register also varies with each product. note: in this product, fosc which is selected by cgosccr by 32 is used as external referrence clock.
page 6-9 TMPM372FWUG 2013/4/15 6.5 interrupts this chapter describes routes, sources and required settings of interrupts. the cpu is notified of interrupt requests by th e interrupt signal from each interrupt source. it sets priority on interrupts and handles an interrupt request with the highest priority. interrupt requests for clearing a standby mode are notified to the cpu via the clock generator. therefore, appropri- ate settings must be made in the clock generator. 6.5.1 interrupt sources 6.5.1.1 interrupt route figure 6-1 shows an interrupt request route. the interrupts issued by the peripheral function that is not used to release standby are directly input to the cpu (route1). the peripheral function interrupts used to release standby (route 2) and interrupts from the external interrupt pin (route 3) are input to the clock generator and are input to the cpu through the logic for releasing standby (route 4 and 5). if interrupts from the external interrupt pins are not us ed to release standby, they are directly input to the cpu, not through the logic for standby release (route 6). figure 6-1 interrupt route 6.5.1.2 generation an interrupt request is generated from an external pin or peripheral function assigned as an interrupt source or by setting the nvic's interrupt set-pending register. peripheral function cpu exiting standby mode clock generator peripheral function interrupt requestq external interrupt pin 0 1 s r t u v port
page 6-10 6. exceptions 6.5 interrupts TMPM372FWUG 2013/4/15 ? from external pin set the port control register so that the external pin can perform as an interrupt function pin. ? from peripheral function set the peripheral function to make it possible to output interrupt requests. see the chapter of each peri pheral function for details. ? by setting interrupt set-pending register (forced pending) an interrupt request can be generated by setting the relevant bit of the interrupt set-pending register. 6.5.1.3 transmission an interrupt signal from an external pin or peripheral function is directly sent to the cpu unless it is used to exit a standby mode. interrupt requests from interrupt sources that can be used for clearing a standb y mode are transmitted to the cpu via the clock generator. for these interrupt sources, appropriate settings must be made in the clock generator in advance. external interrupt sources not used for exiting a standby mode can be used without setting the clock generator. 6.5.1.4 precautions when using external interrupt pins if you use external interrupts, be aware the followings not to generate unexpected interrupts. if input disabled (pxie="0"), inputs from external interrupt pins are "high". also, if external interrupts are not used as a trigger to release standby (route 6 of figure 6-1), input signals from the exter- nal interrupt pins are directly sent to the cpu. si nce the cpu recognizes "hi gh" input as an interrupt, interrupts occur if corresponding interrupts are enabled by the cpu as inputs are being disabled. to use the external interrupt without setting it as a standby trigger, set the interrupt pin input as "low" and enable it. then, enab le interrupts on the cpu.
page 6-11 TMPM372FWUG 2013/4/15 6.5.1.5 list of interrupt sources table 6-3 shows the list of interrupt sources. table 6-3 list of interrupt sources no. interrupt source active level (clearing standby) cg interrupt mode control register 0 reserved - - - 1 reserved - 2 reserved - 3 int3 interrupt pin high/low edge/level selectable cgimcga 4 int4 interrupt pin high/low edge/level selectable cgimcgb 5 int5 interrupt pin 6 intrx0 serial reception (channel0) 7 inttx0 serial transmit (channel0) 8 intrx1 serial reception (channel1) 9 inttx1 serial transmit (channel1) 10 reserved - 11 intvcnb vector engine interrupt b 12 reserved - 13 intemg1 pmd1 emg interrupt 14 reserved - 15 intovv1 pmd1 ovv interrupt 16 reserved - 17 intadbpda adcb conversion tr iggered by pmd0 is finished 18 reserved - 19 intadbpdb adcb conversion tr iggered by pmd1 is finished 20 inttb00 16bit tmrb0 compare match detection 0/ over flow 21 inttb01 16bit tmrb0 compare match detection 1 22 inttb10 16bit tmrb1 compare match detection 0/ over flow 23 inttb11 16bit tmrb1 compare match detection 1 24 inttb40 16bit tmrb4 compare match detection 0/ over flow 25 inttb41 16bit tmrb4 compare match detection 1 26 inttb50 16bit tmrb5 compare match detection 0/ over flow 27 inttb51 16bit tmrb5 compare match detection 1 28 reserved - 29 intpmd1 pmd1 pwm interrupt 30 intcap00 16bit tmrb0 input capture 0 31 intcap01 16bit tmrb0 input capture 1 32 intcap10 16bit tmrb1 input capture 0 33 intcap11 16bit tmrb1 input capture 1 34 intcap40 16bit tmrb4 input capture 0 35 intcap41 16bit tmrb4 input capture 1 36 intcap50 16bit tmrb5 input capture 0
page 6-12 6. exceptions 6.5 interrupts TMPM372FWUG 2013/4/15 37 reserved - 38 int6 interrupt pin high/low edge/level selectable cgimcgb 39 int7 interrupt pin 40 intrx2 serial reception (channel2) 41 inttx2 serial transmit (channel2) 42 reserved - 43 intadbcpa adcb conversion monitoring function interrupt a 44 reserved - 45 intadbcpb adcb conversion monitoring function interrupt b 46 inttb20 16bit tmrb2 compare match detection 0/ over flow 47 inttb21 16bit tmrb2 compare match detection 1 48 inttb30 16bit tmrb3 compare match detection 0/ over flow 49 inttb31 16bit tmrb3 compare match detection 1 50 intcap20 16bit tmrb2 input capture 0 51 intcap21 16bit tmrb2 input capture 1 52 intcap30 16bit tmrb3 input capture 0 53 intcap31 16bit tmrb3 input capture 1 54 reserved - 55 intadbsft adc unit b conversion started by software is fin- ished 56 reserved - 57 intadbtmr adc unit b conversion triggered by timer is finished 58 int8 interrupt pin high/low edge/level selectable cgimcgc 59 reserved - - - 60 reserved - 61 reserved - 62 reserved - 63 intenc1 encoder input1 interrupt 64 intrx3 serial reception (channel3) 65 inttx3 serial transmit (channel3) 66 inttb60 16bit tmrb6 compare match detection 0/ over flow 67 inttb61 16bit tmrb6 compare match detection 1 68 inttb70 16bit tmrb7 compare match detection 0/ over flow 69 inttb71 16bit tmrb7 compare match detection 1 70 intcap60 16bit tmrb6 input capture 0 71 intcap61 16bit tmrb6 input capture 1 72 intcap70 16bit tmrb7 input capture 0 73 intcap71 16bit tmrb7 input capture 1 74 intc interrupt pin high/low edge/level selectable cgimcgd 75 intd interrupt pin 76 inte interrupt pin 77 intf interrupt pin table 6-3 list of interrupt sources no. interrupt source active level (clearing standby) cg interrupt mode control register
page 6-13 TMPM372FWUG 2013/4/15 6.5.1.6 active level the active level indicates which change in signal of an interrupt source trigge rs an interrupt. the cpu recognizes interrupt signals in "high" level as inte rrupt. interrupt signals directly sent from peripheral functions to the cpu are configured to output "high" to indicate an interrupt request. active level is set to the clock generator for interr upts which can be a trigger to release standby. inter- rupt requests from peripheral functio ns are set as rising-edge or fallin g-edge triggered. interrupt requests from interrupt pins can be set as level-sensitive ("hi gh" or "low") or edge-triggered (rising or falling). if an interrupt source is used for clearing a standby mode, setting the relevant clock generator register is also required. enable the cg imcgx bit and specify the active level in the cgim- cgx bits. you must set the active level fo r interrupt requests from each peripheral function as shown in table 6-3 an interrupt request detected by the clock generator is notified to the cpu with a signal in "high" level.
page 6-14 6. exceptions 6.5 interrupts TMPM372FWUG 2013/4/15 6.5.2 interrupt handling 6.5.2.1 flowchart the following shows how an interrupt is handled. the following shows how an exception/interrupt is handled. in the following descriptions, indicates hardware handling. indicates software handling.
page 6-15 TMPM372FWUG 2013/4/15 processing details see setting for detection set the relevant nvic registers for detecting interrupts. set the clock generator as well if each interrupt source is used to clear a standby mode. common setting nvic registers setting to clear standby mode clock generator "6.5.2.2 preparation" setting for sending interrupt signal execute an appropriate setting to send the interrupt signal depending on the interrupt type. setting for interrupt from external pin port setting for interrupt from peripheral function peripheral function (see the chapter of each peripheral function for details.) interrupt generation an interrupt request is generated. interrupt lines used for clearing a stand by mode are connected to the cpu via the clock generator. "6.5.2.3 detection by clock generator" cpu detects interrupt. the cpu detects the interrupt. "6.5.2.4 detection by cpu" if multiple interrupt requests occur simultaneously, the interrupt request with the highest priority is detected according to the priority order. cpu handles interrupt. the cpu handles the interrupt. "6.5.2.5 cpu process- ing" the cpu pushes register contents to the stack before entering the isr. isr execution program for the isr. clear the interrupt source if needed. "6.5.2.6 interrupt service routine (isr)" return to preceding program configure to return to the preceding program of the isr. cg detects interrupt (clearing standby mode) clearing standby mode not clearing standby mode
page 6-16 6. exceptions 6.5 interrupts TMPM372FWUG 2013/4/15 6.5.2.2 preparation when preparing for an interrupt, you need to pay a ttention to the order of configuration to avoid any unexpected interrupt on the way. initiating an interrupt or changing its configuration must be implemented in the following order basi- cally. disable the interrupt by the cp u. configure from the farthest rout e from the cpu. then enable the interrupt by the cpu. to configure the clock generator, you must follow the order indicated here not to cause any unexpected interrupt. first, configure the precondition. secondly, clear the data related to the interrupt in the clock generator and then enable the interrupt. the following sections are listed in the order of in terrupt handling and describe how to configure them. 1. disabling interrupt by cpu 2. cpu registers setting 3. preconfiguration (1) (inter rupt from external pin) 4. preconfiguration (2) (interrupt from peripheral function) 5. preconfiguration (3) (inter rupt set-pending register) 6. configuring the clock generator 7. enabling interrupt by cpu (1) disabling interrupt by cpu to make the cpu for not accepting any interrupt, write "1" to the corresponding bit of the pri- mask register. all interrupts and exceptions other than non-maskable interrupts and hard faults can be masked. use "msr" instruction to set this register. note 1: primask register cannot be modified by the user access level. note 2: if a fault causes when "1" is set to the primask register, it is treated as a hard fault. (2) cpu registers setting you can assign a priority level by writing to field in an interrupt priority register of the nvic register. each interrupt source is provided w ith eight bits for assigning a priority level from 0 to 255, but the number of bits actually used varies with each product.priority level 0 is the highest priority level.if multiple sources have the same priority, the sma llest-numbered interrupt source has the highest prior- ity. you can assign grouping priority by using the in the application interrupt and reset control register. interrupt mask register primask "1"(interrupt disabled)
page 6-17 TMPM372FWUG 2013/4/15 note: "n" indicates the corresponding exceptions/interrupts. this product uses three bits fo r assigning a priority level. (3) preconfiguration (1) (interrupt from external pin) set "1" to the port function register of the corr esponding pin. setting pxfrn[m] allows the pin to be used as the function pin. setting pxie[m] allows the pin to be used as the input port. note: x: port number / m: corresponding bit / n: function register number in modes other than stop mode, setting pxie to enable input enables the co rresponding interrupt input regardless of the pxfr setting. be careful not to enable interrupts that are not used. also, be aware of the descrip- tion of "6.5.1.4 precautions when using external interrupt pins". (4) preconfiguration (2) (interrupt from peripheral function) the setting varies depending on the peripheral function to be used. see the chapter of each periph- eral function for details. (5) preconfiguration (3) (interrupt set-pending register) to generate an interrupt by using the interrupt set-pending register, set "1" to the corresponding bit of this register. note: m: corresponding bit (6) configuring the clock generator for an interrupt source to be used for exiting a standby mode, you need to set the active level and enable interrupts in the cgimcg register of the cl ock generator. the cgimcg register is capable of configuring each source. before enabling an interr upt, clear the corresponding interrupt request already held. this can avoid unexpected interrupt.to clear co rresponding interrupt request, write a value corresponding to the interrupt to be used to the cg icrcg register.see "6.6.3.5 cgi crcg (cg interrupt request clear register)" for each value. nvic register "prioryty" "group priority" (this is configurable if required.) port register pxfrn "1" pxie "1" nvic register interrupt set-pending [m] "1"
page 6-18 6. exceptions 6.5 interrupts TMPM372FWUG 2013/4/15 interrupt requests from external pins can be used without setting the clock generator if they are not used for exiting a standby mode. however, an "high" pulse or "high"-level signal must be input so that the cpu can detect it as an interrupt request. also, be aware of the description of "6.5.1.4 pre- cautions when using external interrupt pins". note: n: register number / m: number assigned to interrupt source (7) enabling interrupt by cpu enable the interrupt by the cpu as shown below. clear the suspended interrupt in the interrupt clear -pending register. enable the intended interrupt with the interrupt set-enable register. each bit of the register is assigned to a single interrupt source. writing "1" to the corresponding bit of the inte rrupt clear-pending register clears the suspended interrupt. writing "1" to the corresponding bit of the interrupt set-enable register enables the intended interrupt. to generate interrupts in the interrupt set-pending register setting, factors to trigger interrupts are lost if pending interrupts are cleared. thus, this operation is not necessary. at the end, primask re gister is zero cleared. note 1: m : corresponding bit note 2: primask register cannot be modified by the user access level. 6.5.2.3 detection by clock generator if an interrupt source is used for exiting a standby mode, an interrupt request is de tected according to the active level specified in the clock ge nerator, and is notified to the cpu. an edge-triggered interrup t request, once detected, is held in the clock generator. a level-sensitive interrupt request must be held at the active level un til it is detected, otherwise the interrupt request will cease to exist when the signal leve l changes from active to inactive. when the clock generator detects an interrupt request, it keeps sending the interrupt signal in "high" level to the cpu until the interrupt request is cleared in the cg interrupt request clear (cgicrcg) reg- ister. if a standby mode is exited without clearing the interrupt request, the same interrupt will be detected again when normal operation is resumed. be sure to clear each interr upt request in the isr. 6.5.2.4 detection by cpu the cpu detects an interrupt requ est with the highest priority. clock generator register cgimcgn active level cgicrcg value corresponding to the interrupt to be used cgimcgn "1" (interrupt enabled) nvic register interrupt clear-pending [m] "1" interrupt set-pending [m] "1" interrupt mask register primask "0"
page 6-19 TMPM372FWUG 2013/4/15 6.5.2.5 cpu processing on detecting an interrupt, the cpu pushes the contents of pc, psr, r0-r3, r12 and lr to the stack then enter the isr. 6.5.2.6 interrupt service routine (isr) an isr requires specific programmi ng according to the application to be used. this section describes what is recommended at the service routin e programming and how the source is cleared. (1) pushing during isr an isr normally pushes register contents to th e stack and handles an in terrupt as required. the cortex-m3 core automatically push es the contents of pc, psr, r0 -r3, r12 and lr to the stack. no extra programming is required for them. push the contents of ot her registers if needed. interrupt requests wi th higher priority and exceptions such as nmi are accepted even when an isr is being executed. we recommend y ou to push the contents of general-purpose registers that might be rewritten. (2) clearing an interrupt source if an interrupt s ource is used for clearing a standby mode, each interrupt request must be cleared with the cg interrupt request clear (cgicrcg) register. if an interrupt source is set as level-sensitive, an interrupt request continues to exist until it is cleared at its source. therefore, the interrupt source must be cl eared. clearing the interrupt source automatically clears the interrupt reque st signal from the clock generator. if an interrupt is set as edge-sensitive, clear an interrupt request by setting the corresponding value in the cgicrcg register. when an active edge occurs again, a new interrupt request will be detected.
page 6-20 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 6.6 exception / interrupt-related registers the cpu's nvic registers and clock generator registers described in this chapter are shown below with their respective addresses. 6.6.1 register list nvic registers base address = 0xe000_e000 register name address systick control and status register 0x0010 systick reload value register 0x0014 systick current value register 0x0018 systick calibration value register 0x001c interrupt set-enable register 1 0x0100 interrupt set-enable register 2 0x0104 interrupt set-enable register 3 0x0108 interrupt clear-enable register 1 0x0180 interrupt clear-enable register 2 0x0184 interrupt clear-enable register 3 0x0188 interrupt set-pending register 1 0x0200 interrupt set-pending register 2 0x0204 interrupt set-pending register 3 0x0208 interrupt clear-pending register 1 0x0280 interrupt clear-pending register 2 0x0284 interrupt clear-pending register 3 0x0288 interrupt priority register 0x0400 ~ 0x0460 vector table offset register 0x0d08 application interrupt and reset control register 0x0d0c system handler priority r egister 0x0d18, 0x0d1c, 0x0d20 system handler control and state register 0x0d24
page 6-21 TMPM372FWUG 2013/4/15 note:access to the "reserved" areas is prohibited. clock generator register base address = 0x4004_0200 register name address cg interrupt request clear register cgicrcg 0x0014 nmi flag register cgnmiflg 0x0018 reset flag register cgrstflg 0x001c cg interrupt mode control register a cgimcga 0x0020 cg interrupt mode control register b cgimcgb 0x0024 cg interrupt mode control register c cgimcgc 0x0028 cg interrupt mode control register d cgimcgd 0x002c reserved - 0x0030 reserved - 0x0034 reserved - 0x0038 reserved - 0x003c
page 6-22 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 6.6.2 nvic registers 6.6.2.1 systick control and status register note: in this product, fosc which is selected by cgoscc r by 32 is used as external referrence clock. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------countflag after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-----clkso urce tickint enable a f t e r r e s e t00000000 bit bit symbol type function 31-17 ? r read as 0. 16 countflag r/w 0: timer not counted to 0 1: timer counted to 0 returns "1" if timer counted to "0" since last time this was read. clears on read of any part of the systick control and status register. 15-3 ? r read as 0. 2 clksource r/w 0: external reference clock (fosc/32) (note) 1: cpu clock (fsys) 1 tickint r/w 0: do not pend systick 1: pend systick 0 enable r/w 0: disable 1: enable if "1" is set, it reloads with the value of the reload value register and starts operation.
page 6-23 TMPM372FWUG 2013/4/15 6.6.2.2 systick reload value register 6.6.2.3 systick correct value register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol reload after reset undefined 15 14 13 12 11 10 9 8 bit symbol reload after reset undefined 7 6 5 4 3 2 1 0 bit symbol reload after reset undefined bit bit symbol type function 31-24 ? r read as 0, 23-0 reload r/w reload value set the value to load into the systick current value register when the timer reaches "0". 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol current after reset undefined 15 14 13 12 11 10 9 8 bit symbol current after reset undefined 7 6 5 4 3 2 1 0 bit symbol current after reset undefined bit bit symbol type function 31-24 ? r read as 0. 23-0 current r/w [read] current systick timer value [write] clear writing to this register with any value clears it to 0. clearing this register also clears the bit of the systick control and status register.
page 6-24 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 6.6.2.4 systick calibration value register note: in the case of a multishot, please use -1. 31 30 29 28 27 26 25 24 bit symbolnorefskew------ after reset00000000 23 22 21 20 19 18 17 16 bit symbol tenms after reset00000000 15 14 13 12 11 10 9 8 bit symbol tenms after reset00001001 7 6 5 4 3 2 1 0 bit symbol tenms after reset11000100 bit bit symbol type function 31 noref r 0: reference clock provided 1: no reference clock 30 skew r 0: calibration value is 10 ms. 1: calibration value is not 10ms. 29-24 ? r read as 0. 23-0 tenms r calibration value reload value to use for 10 ms timing (0xc35) by external reffernce clock. (note)
page 6-25 TMPM372FWUG 2013/4/15 6.6.2.5 interrupt set-enable register 1 31 30 29 28 27 26 25 24 bit symbol setena (interrupt 31) setena (interrupt 30) setena (interrupt 29) - setena (interrupt 27) setena (interrupt 26) setena (interrupt 25) setena (interrupt 24) a f t e r r e s e t00000000 23 22 21 20 19 18 17 16 bit symbol setena (interrupt 23) setena (interrupt 22) setena (interrupt 21) setena (interrupt 20) setena (interrupt 19) - setena (interrupt 17) - a f t e r r e s e t00000000 15 14 13 12 11 10 9 8 bit symbol setena (interrupt 15) - setena (interrupt 13) - setena (interrupt 11) - setena (interrupt 9) setena (interrupt 8) a f t e r r e s e t00000000 7 6 5 4 3 2 1 0 bit symbol setena (interrupt 7) setena (interrupt 6) setena (interrupt 5) setena (interrupt 4) setena (interrupt 3) --- a f t e r r e s e t00000000
page 6-26 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". bit bit symbol type function 31-29 setena r/w interrupt number [31:29] [write] 1: enable [read] 0: disabled 1: enabled each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 28 ? r/w write as 0. 27-19 setena r/w interrupt number [27:19] [write] 1: enable [read] 0: disabled 1: enabled each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 18-16 ? r/w write as 0. 15 setena r/w interrupt number [15] [write] 1: enable [read] 0: disabled 1: enabled each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 14 ? r/w write as 0. 13 setena r/w interrupt number [13] [write] 1: enable [read] 0: disabled 1: enabled each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 12 ? r/w write as 0. 11 setena r/w interrupt number [11] [write] 1: enable [read] 0: disabled 1: enabled each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 10 ? r/w write as 0. 9-3 setena r/w interrupt number [9:3] [write] 1: enable [read] 0: disabled 1: enabled each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 2-0 ? r/w write as 0.
page 6-27 TMPM372FWUG 2013/4/15 6.6.2.6 interrupt set-enable register 2 31 30 29 28 27 26 25 24 bit symbol setena (interrupt 63) ---- setena (interrupt 58) setena (interrupt 57) - a f t e r r e s e t00000000 23 22 21 20 19 18 17 16 bit symbol setena (interrupt 55) - setena (interrupt 53) setena (interrupt 52) setena (interrupt 51) setena (interrupt 50) setena (interrupt 49) setena (interrupt 48) a f t e r r e s e t00000000 15 14 13 12 11 10 9 8 bit symbol setena (interrupt 47) setena (interrupt 46) setena (interrupt 45) - setena (interrupt 43) - setena (interrupt 41) setena (interrupt 40) a f t e r r e s e t00000000 7 6 5 4 3 2 1 0 bit symbol setena (interrupt 39) setena (interrupt 38) - setena (interrupt 36) setena (interrupt 35) setena (interrupt 34) setena (interrupt 33) setena (interrupt 32) a f t e r r e s e t00000000
page 6-28 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 bit bit symbol type function 31 setena r/w interrupt number [63] [write] 1: enable [read] 0: disabled 1: enabled each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 30-27 ? r/w write as 0. 26-25 setena r/w interrupt number [58:57] [write] 1: enable [read] 0: disabled 1: enabled each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 24 ? r/w write as 0. 23 setena r/w interrupt number [55] [write] 1: enable [read] 0: disabled 1: enabled each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 22 ? r/w write as 0. 21-13 setena r/w interrupt number [53:45] [write] 1: enable [read] 0: disabled 1: enabled each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 12 ? r/w write as 0. 11 setena r/w interrupt number [43] [write] 1: enable [read] 0: disabled 1: enabled each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 10 ? r/w write as 0. 9-6 setena r/w interrupt number [41:38] [write] 1: enable [read] 0: disabled 1: enabled each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 5 ? r/w write as 0.
page 6-29 TMPM372FWUG 2013/4/15 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 4-0 setena r/w interrupt number [36:32] [write] 1: enable [read] 0: disabled 1: enabled each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. bit bit symbol type function
page 6-30 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 6.6.2.7 interrupt set-enable register 3 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol - - setena (interrupt 77) setena (interrupt 76) setena (interrupt 75) setena (interrupt 74) setena (interrupt 73) setena (interrupt 72) a f t e r r e s e t00000000 7 6 5 4 3 2 1 0 bit symbol setena (interrupt 71) setena (interrupt 70) setena (interrupt 69) setena (interrupt 68) setena (interrupt 67) setena (interrupt 66) setena (interrupt 65) setena (interrupt 64) a f t e r r e s e t00000000 bit bit symbol type function 31-14 ? r/w read as 0. 13-0 setena r/w interrupt number [77:64] [write] 1: enable [read] 0: disabled 1: enabled each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts.
page 6-31 TMPM372FWUG 2013/4/15 6.6.2.8 interrupt clear-enable register 1 31 30 29 28 27 26 25 24 bit symbol clrena (interrupt 31) clrena (interrupt 30) clrena (interrupt 29) - clrena (interrupt 27) clrena (interrupt 26) clrena (interrupt 25) clrena (interrupt 24) a f t e r r e s e t00000000 23 22 21 20 19 18 17 16 bit symbol clrena (interrupt 23) clrena (interrupt 22) clrena (interrupt 21) clrena (interrupt 20) clrena (interrupt 19) - clrena (interrupt 17) - a f t e r r e s e t00000000 15 14 13 12 11 10 9 8 bit symbol clrena (interrupt 15) - clrena (interrupt 13) - clrena (interrupt 11) - clrena (interrupt 9) clrena (interrupt 8) a f t e r r e s e t00000000 7 6 5 4 3 2 1 0 bit symbol clrena (interrupt 7) clrena (interrupt 6) clrena (interrupt 5) clrena (interrupt 4) clrena (interrupt 3) --- a f t e r r e s e t00000000
page 6-32 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 bit bit symbol type function 31-29 clrena r/w interrupt number [31:29] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 28 ? r/w write as 0. 27-19 clrena r/w interrupt number [27:19] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 18-16 ? r/w write as 0. 15 clrena r/w interrupt number [15] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 14 ? r/w write as 0. 13 clrena r/w interrupt number [13] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 12 ? r/w write as 0. 11 clrena r/w interrupt number [11] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 10 ? r/w write as 0. 9-3 clrena r/w interrupt number [9:3] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 2-0 ? r/w write as 0.
page 6-33 TMPM372FWUG 2013/4/15 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources".
page 6-34 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 6.6.2.9 interrupt clear-enable register 2 31 30 29 28 27 26 25 24 bit symbol clrena (interrupt 63) ---- clrena (interrupt 58) clrena (interrupt 57) - a f t e r r e s e t00000000 23 22 21 20 19 18 17 16 bit symbol clrena (interrupt 55) - clrena (interrupt 53) clrena (interrupt 52) clrena (interrupt 51) clrena (interrupt 50) clrena (interrupt 49) clrena (interrupt 48) a f t e r r e s e t00000000 15 14 13 12 11 10 9 8 bit symbol clrena (interrupt 47) clrena (interrupt 46) clrena (interrupt 45) - clrena (interrupt 43) - clrena (interrupt 41) clrena (interrupt 40) a f t e r r e s e t00000000 7 6 5 4 3 2 1 0 bit symbol clrena (interrupt 39) clrena (interrupt 38) - clrena (interrupt 36) clrena (interrupt 35) clrena (interrupt 34) clrena (interrupt 33) clrena (interrupt 32) a f t e r r e s e t00000000
page 6-35 TMPM372FWUG 2013/4/15 bit bit symbol type function 31 clrena r/w interrupt number [63] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 30-27 ? r/w write as 0. 26-25 clrena r/w interrupt number [58:57] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 24 ? r/w write as 0. 23 clrena r/w interrupt number [55] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 22 ? r/w write as 0. 21-13 clrena r/w interrupt number [53:45] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 12 ? r/w write as 0. 11 clrena r/w interrupt number [43] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 10 ? r/w write as 0. 9-6 clrena r/w interrupt number [41:38] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 5 ? r/w write as 0.
page 6-36 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 4-0 clrena r/w interrupt number [39:32] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. bit bit symbol type function
page 6-37 TMPM372FWUG 2013/4/15 6.6.2.10 interrupt clear-enable register 3 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 6.6.2.11 interrupt set-pending register 1 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol - - clrena (interrupt 77) clrena (interrupt 76) clrena (interrupt 75) clrena (interrupt 74) clrena (interrupt 73) clrena (interrupt 72) a f t e r r e s e t00000000 7 6 5 4 3 2 1 0 bit symbol clrena (interrupt 71) clrena (interrupt 70) clrena (interrupt 69) clrena (interrupt 68) clrena (interrupt 67) clrena (interrupt 66) clrena (interrupt 65) clrena (interrupt 64) a f t e r r e s e t00000000 bit bit symbol type function 31-14 ? r/w read as 0. 13-0 clrena r/w interrupt number [77:64] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 31 30 29 28 27 26 25 24 bit symbol setpend (interrupt 31) setpend (interrupt 30) setpend (interrupt 29) - setpend (interrupt 27) setpend (interrupt 26) setpend (interrupt 25) setpend (interrupt 24) after reset undefined undefined undefined undefined undefined undefined undefined undefined 23 22 21 20 19 18 17 16 bit symbol setpend (interrupt 23) setpend (interrupt 22) setpend (interrupt 21) setpend (interrupt 20) setpend (interrupt 19) - setpend (interrupt 17) - after reset undefined undefined undefined undefined undefined undefined undefined undefined 15 14 13 12 11 10 9 8 bit symbol setpend (interrupt 15) - setpend (interrupt 13) - setpend (interrupt 11) - setpend (interrupt 9) setpend (interrupt 8) after reset undefined undefined undefined undefined undefined undefined undefined undefined 7 6 5 4 3 2 1 0 bit symbol setpend (interrupt 7) setpend (interrupt 6) setpend (interrupt 5) setpend (interrupt 4) setpend (interrupt 3) --- after reset undefined undefined undefined undefined undefined undefined undefined undefined
page 6-38 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 bit bit symbol type function 31-29 setpend r/w interrupt number [31:29] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. writing "1" to a corresponding bit in the interrupt cle ar-pending register clears the bit in this register. 28 ? r/w write as 0. 27-19 setpend r/w interrupt number [27:19] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. writing "1" to a corresponding bit in the interrupt cle ar-pending register clears the bit in this register. 18-16 ? r/w write as 0. 15 setpend r/w interrupt number [15] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. writing "1" to a corresponding bit in the interrupt cle ar-pending register clears the bit in this register. 14 ? r/w write as 0. 13 setpend r/w interrupt number [13] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. writing "1" to a corresponding bit in the interrupt cle ar-pending register clears the bit in this register. 12 ? r/w write as 0. 11 setpend r/w interrupt number [11] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. writing "1" to a corresponding bit in the interrupt cle ar-pending register clears the bit in this register. 10 ? r/w write as 0.
page 6-39 TMPM372FWUG 2013/4/15 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 9-3 setpend r/w interrupt number [9:3] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. writing "1" to a corresponding bit in the interrupt cle ar-pending register clears the bit in this register. 2-0 ? r/w write as 0. bit bit symbol type function
page 6-40 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 6.6.2.12 interrupt set-pending register 2 31 30 29 28 27 26 25 24 bit symbol setpend (interrupt 63) ---- setpend (interrupt 58) setpend (interrupt 57) - after reset undefined undefined undefined undefined undefined undefined undefined undefined 23 22 21 20 19 18 17 16 bit symbol setpend (interrupt 55) - setpend (interrupt 53) setpend (interrupt 52) setpend (interrupt 51) setpend (interrupt 50) setpend (interrupt 49) setpend (interrupt 48) after reset undefined undefined undefined undefined undefined undefined undefined undefined 15 14 13 12 11 10 9 8 bit symbol setpend (interrupt 47) setpend (interrupt 46) setpend (interrupt 45) - setpend (interrupt 43) - setpend (interrupt 41) setpend (interrupt 40) after reset undefined undefined undefined undefined undefined undefined undefined undefined 7 6 5 4 3 2 1 0 bit symbol setpend (interrupt 39) setpend (interrupt 38) - setpend (interrupt 36) setpend (interrupt 35) setpend (interrupt 34) setpend (interrupt 33) setpend (interrupt 32) after reset undefined undefined undefined undefined undefined undefined undefined undefined
page 6-41 TMPM372FWUG 2013/4/15 bit bit symbol type function 31 setpend r/w interrupt number [63] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. writing "1" to a corresponding bit in the interrupt cle ar-pending register clears the bit in this register. 30-27 ? r/w write as 0. 26-25 setpend r/w interrupt number [58:57] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. writing "1" to a corresponding bit in the interrupt cle ar-pending register clears the bit in this register. 24 ? r/w write as 0. 23 setpend r/w interrupt number [55] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. writing "1" to a corresponding bit in the interrupt cle ar-pending register clears the bit in this register. 22 ? r/w write as 0. 21-13 setpend r/w interrupt number [53:45] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. writing "1" to a corresponding bit in the interrupt cle ar-pending register clears the bit in this register. 12 ? r/w write as 0. 11 setpend r/w interrupt number [43] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. writing "1" to a corresponding bit in the interrupt cle ar-pending register clears the bit in this register. 10 ? r/w write as 0.
page 6-42 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 9-6 setpend r/w interrupt number [41:38] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. writing "1" to a corresponding bit in the interrupt cle ar-pending register clears the bit in this register. 5 ? r/w write as 0. 4-0 setpend r/w interrupt number [36:32] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. writing "1" to a corresponding bit in the interrupt cle ar-pending register clears the bit in this register. bit bit symbol type function
page 6-43 TMPM372FWUG 2013/4/15 6.6.2.13 interrupt set-pending register 3 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 31 30 29 28 27 26 25 24 bit symbol-------- after reset undefined undefined undefined undefined undefined undefined undefined undefined 23 22 21 20 19 18 17 16 bit symbol-------- after reset undefined undefined undefined undefined undefined undefined undefined undefined 15 14 13 12 11 10 9 8 bit symbol - - setpend (interrupt 77) setpend (interrupt 76) setpend (interrupt 75) setpend (interrupt 74) setpend (interrupt 73) setpend (interrupt 72) after reset undefined undefined undefined undefined undefined undefined undefined undefined 7 6 5 4 3 2 1 0 bit symbol setpend (interrupt 71) setpend (interrupt 70) setpend (interrupt 69) setpend (interrupt 68) setpend (interrupt 67) setpend (interrupt 66) setpend (interrupt 65) setpend (interrupt 64) after reset undefined undefined undefined undefined undefined undefined undefined undefined bit bit symbol type function 31-14 ? r/w read as 0. 13-0 setpend r/w interrupt number [77:64] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. writing "1" to a corresponding bit in the interrupt cle ar-pending register clears the bit in this register.
page 6-44 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 6.6.2.14 interrupt clear-pending register 1 31 30 29 28 27 26 25 24 bit symbol clrpend (interrupt 31) clrpend (interrupt 30) clrpend (interrupt 29) - clrpend (interrupt 27) clrpend (interrupt 26) clrpend (interrupt 25) clrpend (interrupt 24) after reset undefined undefined undefined undefined undefined undefined undefined undefined 23 22 21 20 19 18 17 16 bit symbol clrpend (interrupt 23) clrpend (interrupt 22) clrpend (interrupt 21) clrpend (interrupt 20) clrpend (interrupt 19) - clrpend (interrupt 17) - after reset undefined undefined undefined undefined undefined undefined undefined undefined 15 14 13 12 11 10 9 8 bit symbol clrpend (interrupt 15) - clrpend (interrupt 13) - clrpend (interrupt 11) - clrpend (interrupt 9) clrpend (interrupt 8) after reset undefined undefined undefined undefined undefined undefined undefined undefined 7 6 5 4 3 2 1 0 bit symbol clrpend (interrupt 7) clrpend (interrupt 6) clrpend (interrupt 5) clrpend (interrupt 4) clrpend (interrupt 3) --- after reset undefined undefined undefined undefined undefined undefined undefined undefined
page 6-45 TMPM372FWUG 2013/4/15 bit bit symbol type function 31-29 clrpend r/w interrupt number [31:29] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the correspo nding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. 28 ? r/w write as 0. 27-19 clrpend r/w interrupt number [27:19] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the correspo nding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. 18-16 ? r/w write as 0. 15 clrpend r/w interrupt number [15] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the correspo nding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. 14 ? r/w write as 0. 13 clrpend r/w interrupt number [13] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the correspo nding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. 12 ? r/w write as 0. 11 clrpend r/w interrupt number [11] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the correspo nding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. 10 ? r/w write as 0.
page 6-46 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 9-3 clrpend r/w interrupt number [9:3] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the correspo nding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. 2-0 ? r/w write as 0. bit bit symbol type function
page 6-47 TMPM372FWUG 2013/4/15 6.6.2.15 interrupt clear-pending register 2 31 30 29 28 27 26 25 24 bit symbol clrpend (interrupt 63) ---- clrpend (interrupt 58) clrpend (interrupt 57) - after reset undefined undefined undefined undefined undefined undefined undefined undefined 23 22 21 20 19 18 17 16 bit symbol clrpend (interrupt 55) - clrpend (interrupt 53) clrpend (interrupt 52) clrpend (interrupt 51) clrpend (interrupt 50) clrpend (interrupt 49) clrpend (interrupt 48) after reset undefined undefined undefined undefined undefined undefined undefined undefined 15 14 13 12 11 10 9 8 bit symbol clrpend (interrupt 47) clrpend (interrupt 46) clrpend (interrupt 45) - clrpend (interrupt 43) - clrpend (interrupt 41) clrpend (interrupt 40) after reset undefined undefined undefined undefined undefined undefined undefined undefined 7 6 5 4 3 2 1 0 bit symbol clrpend (interrupt 39) clrpend (interrupt 38) - clrpend (interrupt 36) clrpend (interrupt 35) clrpend (interrupt 34) clrpend (interrupt 33) clrpend (interrupt 32) after reset undefined undefined undefined undefined undefined undefined undefined undefined
page 6-48 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 bit bit symbol type function 31 clrpend r/w interrupt number [63] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the correspo nding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. 30-27 ? r/w write as 0. 26-25 clrpend r/w interrupt number [58:57] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the correspo nding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. 24 ? r/w write as 0. 23 clrpend r/w interrupt number [55] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the correspo nding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. 22 ? r/w write as 0. 21-13 clrpend r/w interrupt number [53:45] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the correspo nding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. 12 ? r/w write as 0. 11 clrpend r/w interrupt number [43] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the correspo nding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. 10 ? r/w write as 0.
page 6-49 TMPM372FWUG 2013/4/15 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 6.6.2.16 interrupt clear-pending register 3 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 9-6 clrpend r/w interrupt number [41:38] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the correspo nding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. 5 ? r/w write as 0. 4-0 clrpend r/w interrupt number [36:32] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the correspo nding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. 31 30 29 28 27 26 25 24 bit symbol-------- after reset undefined undefined undefined undefined undefined undefined undefined undefined 23 22 21 20 19 18 17 16 bit symbol-------- after reset undefined undefined undefined undefined undefined undefined undefined undefined 15 14 13 12 11 10 9 8 bit symbol - - clrpend (interrupt 77) clrpend (interrupt 76) clrpend (interrupt 75) clrpend (interrupt 74) clrpend (interrupt 73) clrpend (interrupt 72) after reset undefined undefined undefined undefined undefined undefined undefined undefined 7 6 5 4 3 2 1 0 bit symbol clrpend (interrupt 71) clrpend (interrupt 70) clrpend (interrupt 69) clrpend (interrupt 68) clrpend (interrupt 67) clrpend (interrupt 66) clrpend (interrupt 65) clrpend (interrupt 64) after reset undefined undefined undefined undefined undefined undefined undefined undefined bit bit symbol type function 31-14 ? r/w read as 0. 13-0 clrpend r/w interrupt number [77:64] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the correspo nding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. bit bit symbol type function
page 6-50 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 6.6.2.17 interrupt priority register each interrupt is provided with eight b its of an interrupt priority register. the following shows the addresses of the interrupt priority registers corresponding to interrupt num- bers. the number of bits to be used for assigning a priori ty varies with each product. this product uses three bits for assigning a priority. the following shows the fields of the interrupt prior ity registers for interrupt numbers 0 to 3. the inter- rupt priority registers for all other interrupt numbers have the identical fields . unused bits return "0" when read, and writing to unused bits has no effect. 31 24 23 16 15 8 7 0 0xe000_e400 pri_3 ??? 0xe000_e404 pri_7 pri_6 pri_5 pri_4 0xe000_e408 pri_11 ? pri_9 pri_8 0xe000_e40c pri_15 ? pri_13 ? 0xe000_e410 pri_19 ? pri_17 ? 0xe000_e414 pri_23 pri_22 pri_21 pri_20 0xe000_e418 pri_27 pri_26 pri_25 pri_24 0xe000_e41c pri_31 pri_30 pri_29 ? 0xe000_e420 pri_35 pri_34 pri_33 pri_32 0xe000_e424 pri_39 pri_38 ? pri_36 0xe000_e428 pri_43 ? pri_41 pri_40 0xe000_e42c pri_47 pri_46 pri_45 ? 0xe000_e430 pri_51 pri_50 pri_49 pri_48 0xe000_e434 pri_55 ? pri_53 pri_52 0xe000_e438 ? pri_58 pri_57 ? 0xe000_e43c pri_63 ??? 0xe000_e440 pri_67 pri_66 pri_65 pri_64 0xe000_e444 pri_71 pri_70 pri_69 pri_68 0xe000_e448 pri_75 pri_74 pri_73 pri_72 0xe000_e44c ?? pri_77 pri_76 31 30 29 28 27 26 25 24 bit symbol pri_3 ????? a f t e r r e s e t00000000 23 22 21 20 19 18 17 16 bit symbol pri_2 ????? a f t e r r e s e t00000000 15 14 13 12 11 10 9 8 bit symbol pri_1 ????? a f t e r r e s e t00000000 7 6 5 4 3 2 1 0 bit symbol pri_0 ????? a f t e r r e s e t00000000
page 6-51 TMPM372FWUG 2013/4/15 bit bit symbol type function 31-29 pri_3 r/w priority of interrupt number 3 28-24 ? r read as 0, 23-21 pri_2 r/w priority of interrupt number 2 20-16 ? r read as 0, 15-13 pri_1 r/w priority of interrupt number 1 12-8 ? r read as 0, 7-5 pri_0 r/w priority of interrupt number 0 4-0 ? r read as 0,
page 6-52 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 6.6.2.18 vector table offset register 31 30 29 28 27 26 25 24 bit symbol - - tblbase tbloff after reset00000000 23 22 21 20 19 18 17 16 bit symbol tbloff after reset00000000 15 14 13 12 11 10 9 8 bit symbol tbloff after reset00000000 7 6 5 4 3 2 1 0 bit symboltbloff------- after reset00000000 bit bit symbol type function 31-30 ? r read as 0, 29 tblbase r/w table base the vector table is in: 0 : code space 1: sram space 28-7 tbloff r/w offset value set the offset value from the top of the space specified in tblbase. the offset must be aligned based on the number of exce ptions in the table.this means that the minimum align- ment is 32 words that you can use for up to 16 interrupt s.for more interrupts, you must adjust the alignment by rounding up to the next power of two. 6-0 ? r read as 0,
page 6-53 TMPM372FWUG 2013/4/15 6.6.2.19 application interrupt and reset control register note 1: little-endian is the default memory format for this product. note 2: when sysresetreq is output, warm reset is pe rformed on this product. is cleared by warm reset. 31 30 29 28 27 26 25 24 bit symbol vectkey/vectkeystat after reset00000000 23 22 21 20 19 18 17 16 bit symbol vectkey/vectkeystat after reset00000000 15 14 13 12 11 10 9 8 bit symbolendianess---- prigroup after reset00000000 7 6 5 4 3 2 1 0 b i t s y m b o l----- sysreset req vectclr active vectreset a f t e r r e s e t00000000 bit bit symbol type function 31-16 vectkey (written) / vectkeystat (read) r/w register key [write] writing to this register requires 0x5fa in the field. [read] read as 0xfa05. 15 endianess r/w endianness bit: (note1) 1: big endian 0: little endianl 14-11 ? r read as 0, 10-8 prigroup r/w interrupt priority grouping 000: seven bits of pre-emption priority, one bit of subpriority 001: six bits of pre-emption priority, two bits of subpriority 010: five bits of pre-emption priority, three bits of subpriority 011: four bits of pre-emption priority, four bits of subpriority 100: three bits of pre-emption priority, five bits of subpriority 101: two bits of pre-emption priority, six bits of subpriority 110: one bit of pre-emption priority, seven bits of subpriority 111: no pre-emption priority, eight bits of subpriority the bit configuration to split the interrupt priority regi ster into pre-emption priority and sub priority. 7-3 ? r read as 0, 2 sysreset req r/w system reset request 1=cpu outputs a sysresetreq signal. (note2) 1vectclr active r/w clear active vector bit 1: clear all state information for active nmi, fault, and interrupts. 0: do not clear. this bit self-clears. it it the responsibility of the a pplication to reinitialize the stack. 0 vectreset r/w system reset bit 1: reset system. 0: do not reset system. resets the system, with the exception of debug component s (fpb, dwt and itm) by setting "1" and this bit is also zero cleared.
page 6-54 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 6.6.2.20 system handler priority register each exception is provided with eight bits of a system handler priority register. the following shows the addresses of the system handler priority registers corresponding to each exception. the number of bits to be used for assigning a priori ty varies with each product. this product uses three bits for assigning a priority. the following shows the fields of the system handler priority regi sters for memory management, bus fault and usage fault. unused bits return "0" when read, and writing to unused bits has no effect. 31 24 23 16 15 8 7 0 0xe000_ed18 pri_7 pri_6 (usage fault) pri_5 (bus fault) pri_4 (memory management) 0xe000_ed1c pri_11 (svcall) pri_10 pri_9 pri_8 0xe000_ed20 pri_15 (systick) pri_14 (pendsv) pri_13 pri_12 (debug monitor) 31 30 29 28 27 26 25 24 bit symbol pri_7 ----- after reset00000000 23 22 21 20 19 18 17 16 bit symbol pri_6 ----- after reset00000000 15 14 13 12 11 10 9 8 bit symbol pri_5 ----- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pri_4 ----- after reset00000000 bit bit symbol type function 31-29 pri_7 r/w reserved 28-24 ? r read as 0, 23-21 pri_6 r/w priority of usage fault 20-16 ? r read as 0, 15-13 pri_5 r/w priority of bus fault 12-8 ? r read as 0, 7-5 pri_4 r/w priority of memory management 4-0 ? r read as 0,
page 6-55 TMPM372FWUG 2013/4/15 6.6.2.21 system handler control and state register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 b i t s y m b o l----- usgfault ena busfault ena memfault ena a f t e r r e s e t00000000 15 14 13 12 11 10 9 8 bit symbol svcall pended busfault pended memfault pended usgfault pended systickact pendsvact - monitor act a f t e r r e s e t00000000 7 6 5 4 3 2 1 0 bit symbol svcallact - - - usgfault act - busfault act memfault act a f t e r r e s e t00000000
page 6-56 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 note: you must clear or set the active bits with extreme caut ion because clearing and setting thes e bits does not repair stack c on- tents. bit bit symbol type function 31-19 ? r read as 0, 18 usgfault ena r/w usage fault 0: disabled 1: enabled 17 busfaul tena r/w bus fault 0: disable 1: enable 16 memfault ena r/w memory management 0: disable 1: enable 15 svcall pended r/w svcall 0: not pended 1: pended 14 busfault pended r/w bus fault 0: not pended 1: pended 13 memfault pended r/w memory management 0: not pended 1: pended 12 usgfault pended r/w usage fault 0: not pended 1: pended 11 systickact r/w systick 0: inactive 1: active 10 pendsvact r/w pendsv 0: inactive 1: active 9 ? r read as 0, 8 monitoract r/w debug monitor 0: inactive 1: active 7 svcallact r/w svcall 0: inactive 1: active 6-4 ? r read as 0, 3usgfault act r/w usage fault 0: inactive 1: active 2 ? r read as 0, 1 busfault act r/w bus fault 0: inactive 1: active 0memfault act r/w memory management 0: inactive 1: active
page 6-57 TMPM372FWUG 2013/4/15 6.6.3 clock generator registers 6.6.3.1 cgimcga (cg interrupt mode control register a) 31 30 29 28 27 26 25 24 bit symbol - emcg3 emst3 - int3en after reset001000undefined0 23 22 21 20 19 18 17 16 bit symbol----- -- after reset001000undefined0 15 14 13 12 11 10 9 8 bit symbol----- -- after reset001000undefined0 7 6 5 4 3 2 1 0 bit symbol----- -- after reset001000undefined0 bit bit symbol type function 31 ? r read as 0. 30-28 emcg3[2:0] r/w active level setting of int3 standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 27-26 emst3[1:0] r active level of int3 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 25 ? r reads as undefined. 24 int3en r/w int3 clear input 0: disable 1: enable 23 ? r read as 0. 22-20 ? r/w write optional value. 19-18 ? r read as 0. 17 ? r read as undefined. 16 ? r/w write as 0. 15 ? r read as 0. 14-12 ? r/w write optional value. 11-10 ? r read as 0. 9 ? r read as undefined. 8 ? r/w write as 0. 7 ? r read as 0. 6-4 ? r/w write optional value. 3-2 ? r read as 0. 1 ? r read as undefined. 0 ? r/w write as 0.
page 6-58 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 note 1: is effective only when is set to "100" for both rising and falling edge. the active level used for the reset of standby can be checked by referring . if interrupts are cleared with the cgicrcg register, is also cleared. note 2: please specify the bit for the edge first and then specify the bit for the . setting them simultaneously is proh ib- ited.
page 6-59 TMPM372FWUG 2013/4/15 6.6.3.2 cgimcgb (cg interrupt mode control register b) 31 30 29 28 27 26 25 24 bit symbol - emcg7 emst7 - int7en after reset001000undefined0 23 22 21 20 19 18 17 16 bit symbol - emcg6 emst6 - int6en after reset001000undefined0 15 14 13 12 11 10 9 8 bit symbol - emcg5 emst5 - int5en after reset001000undefined0 7 6 5 4 3 2 1 0 bit symbol - emcg4 emst4 - int4en after reset001000undefined0
page 6-60 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15
page 6-61 TMPM372FWUG 2013/4/15 bit bit symbol type function 31 ? r read as 0. 30-28 emcg7[2:0] r/w active level setting of int7 standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 27-26 emst7[1:0] r active level of int7 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 25 ? r reads as undefined. 24 int7en r/w int7 clear input 0: disable 1: enable 23 ? r read as 0. 22-20 emcg6[2:0] r/w active level setting of int6 standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 19-18 emst6[1:0] r active level of int6 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 17 ? r reads as undefined. 16 int6en r/w int6 clear input 0:disable 1: enable 15 ? r read as 0. 14-12 emcg5[2:0] r/w active level setting of int5 standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 11-10 emst5[1:0] r active level of int5 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 9 ? r reads as undefined. 8 int5en r/w int5 clear input 0: disable 1: enable 7 ? r read as 0. 6-4 emcg4[2:0] r/w active level setting of int4 standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 3-2 emst4[1:0] r active level of int4 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 1 ? r reads as undefined.
page 6-62 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 note 1: is effective only when is set to "100" for both rising and falling edge. the active level used for the reset of standby can be checked by referring . if interrupts are cleared with the cgicrcg register, is also cleared. note 2: please specify the bit for the edge first and then specify the bit for the . setting them simultaneously is proh ib- ited. 0 int4en r/w int4 clear input 0: disable 1: enable bit bit symbol type function
page 6-63 TMPM372FWUG 2013/4/15 6.6.3.3 cgimcgc (cg interrupt mode control register c) note 1: is effective only when is set to "100" for both rising and falling edge. the active level used for the reset of standby can be checked by referring . if interrupts are cleared with the cgicrcg register, is also cleared. 31 30 29 28 27 26 25 24 bit symbol-------- after reset001000undefined0 23 22 21 20 19 18 17 16 bit symbol-------- after reset001000undefined0 15 14 13 12 11 10 9 8 bit symbol-------- after reset001000undefined0 7 6 5 4 3 2 1 0 bit symbol - emcg8 emst8 - int8en after reset001000undefined0 bit bit symbol type function 31 ? r read as 0. 30-28 ? r/w write optional value. 27-26 ? r read as 0. 25 ? r read as undefined. 24 ? r/w write as 0. 23 ? r read as 0. 22-20 ? r/w write optional value. 19-18 ? r read as 0. 17 ? r read as undefined. 16 ? r/w write as 0. 15 ? r read as 0. 14-12 ? r/w write optional value. 11-10 ? r read as 0. 9 ? r read as undefined. 8 ? r/w write as 0. 7 ? r read as 0. 6-4 emcg8[2:0] r/w active level setting of int8 standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 3-2 emst8[1:0] r active level of int8 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 1 ? r reads as undefined. 0 int8en r/w int8 clear input 0: disable 1: enable
page 6-64 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 note 2: please specify the bit for the edge first and then specify the bit for the . setting them simultaneously is proh ib- ited. 6.6.3.4 cgimcgd (cg interrupt mode control register d) 31 30 29 28 27 26 25 24 bit symbol - emcgf emstf - intfen after reset001000undefined0 23 22 21 20 19 18 17 16 bit symbol - emcge emste - inteen after reset001000undefined0 15 14 13 12 11 10 9 8 bit symbol - emcgd emstd - intden after reset001000undefined0 7 6 5 4 3 2 1 0 bit symbol - emcgc emstc - intcen after reset001000undefined0
page 6-65 TMPM372FWUG 2013/4/15 bit bit symbol type function 31 ? r read as 0. 30-28 emcgf[2:0] r/w active level setting of intf standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 27-26 emstf[1:0] r active level of intf standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 25 ? r reads as undefined. 24 intfen r/w intf clear input 0: disable 1: enable 23 ? r read as 0. 22-20 emcge[2:0] r/w active level setting of inte standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 19-18 emste[1:0] r active level of inte standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 17 ? r reads as undefined. 16 inteen r/w inte clear input 0: disable 1: enable 15 ? r read as 0. 14-12 emcgd[2:0] r/w active level setting of intd standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 11-10 emstd[1:0] r active level of intd standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 9 ? r reads as undefined. 8 intden r/w intd clear input 0: disable 1: enable 7 ? r read as 0. 6-4 emcgc[2:0] r/w active level setting of intc standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 3-2 emstc[1:0] r active level of intc standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 1 ? r reads as undefined.
page 6-66 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 note 1: is effective only when is set to "100" for both rising and falling edge. the active level used for the reset of standby can be checked by referring . if interrupts are cleared with the cgicrcg register, is also cleared. note 2: please specify the bit for the edge first and then specify the bit for the . setting them simultaneously is proh ib- ited. 0 intcen r/w intc clear input 0: disable 1: enable bit bit symbol type function
page 6-67 TMPM372FWUG 2013/4/15 6.6.3.5 cgicrcg (cg interrupt request clear register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - icrcg after reset00000000 bit bit symbol type function 31-5 ? r read as 0, 4-0 icrcg[4:0] w clear interrupt requests. 0_0000:reserved 0_1000: int8 0_0001: reserved 0_1001: reserved 0_0010: reserved 0_1010:reserved 0_0011: int3 0_1011: reserved 0_0100: int4 0_1100:intc 0_0101: int5 0_1101: intd 0_0110: int6 0_1110: inte 0_ 0111: int7 0_1111: intf 1_0000 to 1_ 1111: reserved read as 0.
page 6-68 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15 6.6.3.6 cgnmiflg (nmi flag register) note: are cleared to "0" when they are read. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-------nmiflg0 after reset00000000 bit bit symbol type function 31-1 ? r read as 0. 0 nmiflg0 r nmi source generation flag 0: not applicable 1: generated from wdt
page 6-69 TMPM372FWUG 2013/4/15 6.6.3.7 cgrstflg (reset flag register) note 1: this flag indicates a reset generated by the sysresetreq bit of the application interrupt and reset control register of the cpu's nvic. note 2: this product has power-on reset circui t and this register is initialized only by power-on reset. therefore, "1" is set t o the bit in initial reset state right after power-on. note that this bit is not set by the second and subsequent resets and this register is not cleared automatically. write "0" to clear the register. 31 30 29 28 27 26 25 24 b i t s y m b o l-------- after power-on reset 00000000 23 22 21 20 19 18 17 16 b i t s y m b o l-------- after power-on reset 00000000 15 14 13 12 11 10 9 8 b i t s y m b o l-------- after power-on reset 00000000 7 6 5 4 3 2 1 0 bit symbol - - ofdrstf dbgrstf vltdrstf wdtrstf pinrstf ponrstf after power-on reset 00000001 bit bit symbol type function 31-6 ? r read as 0. 5 ofdrstf r/w ofd reset flag (note1) 0: "0" is written 1: reset from ofd 4 dbgrstf r/w debug reset flag (note1) 0: "0" is written 1: reset from sysresetreq 3 vltdrstf r/w vltd reset flag 0: "0" is written 1: reset from vltd 2 wdtrstf r/w wdt reset flag 0: "0" is written 1: reset from wdt 1 pinrstf r/w reset pin flag 0: "0" is written 1: reset from reset pin 0 ponrstf r/w power-on flag 0: "0" is written 1: reset from power-on reset
page 6-70 6. exceptions 6.6 exception / interrupt-related registers TMPM372FWUG 2013/4/15
page 7-1 TMPM372FWUG 2013/4/15 7. internal high-speed oscill ation adjustment function TMPM372FWUG has the internal high-speed oscillation adjustment function. note: this adjustment function is not app licable to the reference clock for ofd. 7.1 structure the internal oscillation adjustment function uses the pulse width measurement function of 16-bit timer/event counter (tmrb). figure 7-1 shows the function configuration. figure 7-1 functi on block diagram cpu tmrb internal high-speed oscillator trimoscinit trimoscset trimoscen clock initial vaiue read trimming data set capture interrupt %crvwtgtgikuvgttgcf tbxin
page 7-2 7. internal high-speed oscillation adjustment func- tion 7.2 registers TMPM372FWUG 2013/4/15 7.2 registers 7.2.1 register list the control registers and its addresses are as follows. 7.2.2 trmoscpro (p rotect register) base address = 0x4004 _ 0300 register name address(base+) protect register trmoscpro 0x0000 enable register trmoscen 0x0004 initial trimming value monitoring register trmoscinit 0x0008 trimming value setting register trmoscset 0x000c 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol protect after reset00000000 bit bit symbol type ?@?\ 31-8 ? r read as "0". 7-0 ? r/w writing register control 0xc1 : enable other than 0xc1 : desable when "0xc1" is set, trmoscen, trmoscin it and trmoscset are allowed to write.
page 7-3 TMPM372FWUG 2013/4/15 7.2.3 trmoscen (e nable register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-----tbprun-tbrun after reset00000000 bit bit symbol type ?@?\ 31-1 ? r read as "0". 0 trimen r/w trimming control 0 : disable 1 : enable when "1" is set, a trimming value of the internal oscillator is switched from a value of trimoscinit to a value of trmoscset.
page 7-4 7. internal high-speed oscillation adjustment func- tion 7.2 registers TMPM372FWUG 2013/4/15 7.2.4 trmoscinit (initial tr imming value monitor register) for details about the specific setting and adjustment va lue of coarse trimming and fine trimming, refer to "table 7-1 adjustment range". 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol - - triminitc after reset 0 0 undifined 7 6 5 4 3 2 1 0 bit symbol---- triminitf after reset0000 undifined bit bit symbol type ?@?\ 31-14 ? r read as "0". 13-8 triminitc r/w initial coarse trimmng value enables to monitor initial coarse trimming value. 7-4 ? r read as "0". 3-0 triminitf r/w initial fine trimming value enables to monitor initial fine trimming value.
page 7-5 TMPM372FWUG 2013/4/15 7.2.5 trmoscset (trimmin g value setting register) for details about the specific setting and adjustment va lue of coarse trimming and fine trimming, refer to "table 7-1 adjustment range". 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol - - trimsetc after reset00000000 7 6 5 4 3 2 1 0 bit symbol---- trimsetf after reset00100000 bit bit symbol type ?@?\ 31-14 ? r read as "0". 13-8 tbrswr r/w coarse trimmng value setting sets the coarse trimming value. 7-4 ? r read as "0". 3-0 tbclk[1:0] r/w fine trimmng value setting sets the fine trimming value.
page 7-6 7. internal high-speed oscillation adjustment func- tion 7.3 operational description TMPM372FWUG 2013/4/15 7.3 operational description 7.3.1 outline oscillation is adjusted using coarse trim ming values and fine trimming values. the value setting before shipping can be check ed with trmoscinit and . when the value changing, set a new value to trmo scset and . by setting "1" to trmoscen, a setting value of the internal oscillator will be changed. note:after reset, writing to trmoscset and trmoscen is prohibited. when writing to these bits, trmoscpro must be set to "0xc1". 7.3.2 adjustment range in the coarse trimming, ? 57.6% to + 55.8% adjustment by 1.8%-step is feasible. in the fine trimming, ? 2.4% to + 2.1% adjustment by 0.3%-step is feasible. table 7-1 shows a adjustment range. note:each step value is assumed based on the typi cal condition. in the coarse trimming, it has 0.2% margin of error. in the fine trimming, it has 0.1% margin of error. 7.3.3 internal oscillation frequency measurement using tmrb to measure a frequency of high-speed oscillator, the pulse width measurement function of tmrb can be used. first, choose an internal oscillator as a prescaler clock t0 of tmrb. second, input a pulse from tbxin. third, capture an up-counter value at the rising edge of the pulse using the capture function. finally, determine the adjustment value using a difference between a frequency of tbxin calculated with capture value and the actual frequency. table 7-1 adjustment range coarse trimming fine trimming frequency change (typ.) frequency change (typ.) 011111 + 55.8% 0111 + 2.1% ?? ?? 000001 + 1.8% 0001 + 0.3% 000000 0% 0000 0% 111111 ? 1.8% 1111 ? 0.3% 111110 ? 3.6% 1110 ? 0.6% ?? ?? 100000 ? 57.6% 1000 ? 2.4%
page 8-1 TMPM372FWUG 2013/4/15 8. input / output ports 8.1 port functions 8.1.1 function list TMPM372FWUG has 53 ports.besides the ports function, these ports can be used as i/o pins for peripheral functions. table 8-1 shows the port function table. table 8-1 port function list port pin input /out- put pull-up pull-down schmitt input noise fil- ter program- mable open- drain function pin porta pa0 i/o pull-up / pull-down ?? tb0in , int3 pa1 i/o pull-up / pull-down - tb0out pa2 i/o pull-up / pull-down ?? tb1in , int4 pa3 i/o pull-up / pull-down - tb1out pa4 i/o pull-up / pull-down - sclk1 , cts1 pa5 i/o pull-up / pull-down - txd1 , tb6out pa6 i/o pull-up / pull-down - rxd1 , tb6in pa7 i/o pull-up / pull-down ?? tb4in , int8 portb pb0 i/o pull-up / pull-down - traceclk pb1 i/o pull-up / pull-down - tracedata0 pb2 i/o pull-up / pull-down - tracedata1 pb3 i/o pull-up / pull-down - tms / swdio pb4 i/o pull-up / pull-down - tck / swclk pb5 i/o pull-up / pull-down - tdo / swv pb6 i/o pull-up / pull-down - tdi pb7 i/o pull-up / pull-down ?? trst portd pd4 i/o pull-up / pull-down - sclk2 , cts2 pd5 i/o pull-up / pull-down - txd2 pd6 i/o pull-up / pull-down - rxd2 porte pe0 i/o pull-up / pull-down - txd0 pe1 i/o pull-up / pull-down - rxd0 pe2 i/o pull-up / pull-down - sclk0 , cts0 pe3 i/o pull-up / pull-down - tb4out pe4 i/o pull-up / pull-down ?? tb2in , int5 pe5 i/o pull-up / pull-down - tb2out : exist - : not exist
page 8-2 8. input / output ports 8.1 port functions TMPM372FWUG 2013/4/15 note:the noise elimination width of the noise fi lter is approximately 30 ns under typical conditions. pe6 i/o pull-up / pull-down ?? tb3in , int6 pe7 i/o pull-up / pull-down ?? tb3out , int7 portf pf0 i/o pull-up / pull-down - tb7in , boot pf1 i/o pull-up / pull-down - tb7out pf2 i/o pull-up / pull-down - enca1 , sclk3 , cts3 pf3 i/o pull-up / pull-down - encb1 , txd3 pf4 i/o pull-up / pull-down - encz1 , rxd3 portg pg0 i/o pull-up / pull-down - uo1 pg1 i/o pull-up / pull-down - xo1 pg2 i/o pull-up / pull-down - vo1 pg3 i/o pull-up / pull-down - yo1 pg4 i/o pull-up / pull-down - wo1 pg5 i/o pull-up / pull-down - zo1 pg6 i/o pull-up / pull-down - emg1 pg7 i/o pull-up / pull-down - ovv1 porti pi3 i/o pull-up / pull-down - aina11 / ainb2 portj pj0 i/o pull-up / pull-down - ainb3 pj1 i/o pull-up / pull-down - ainb4 pj2 i/o pull-up / pull-down - ainb5 pj3 i/o pull-up / pull-down - ainb6 pj4 i/o pull-up / pull-down - ainb7 pj5 i/o pull-up / pull-down - ainb8 pj6 i/o pull-up / pull-down ?? intc , ainb9 pj7 i/o pull-up / pull-down ?? intd , ainb10 portk pk0 i/o pull-up / pull-down ?? inte , ainb11 pk1 i/o pull-up / pull-down ?? intf , ainb12 portm pm0 i/o pull-up / pull-down - x1 pm1 i/o pull-up / pull-down - x2 table 8-1 port function list port pin input /out- put pull-up pull-down schmitt input noise fil- ter program- mable open- drain function pin : exist - : not exist
page 8-3 TMPM372FWUG 2013/4/15 8.1.2 port registers outline the following registers need to be configured to use ports. ? pxdata: port x data register to read / write port data. ? pxcr: port x output control register to control output. pxie needs to be configured to control input. ? pxfrn: port x function register n to set function. an assigned function can be activated by setting "1". ? pxod: port x open drain control register to control the programmable open drain. programmable open drain is function to be mate rialized pseudo-open-drain by setting the pxod. when pxod is set "1",output buffer is disabled and pseudo-open-drain is materialized. ? pxpup: port x pull-up control register to control programmable pull ups. ? pxpdn: port x pull-down control register to control programmable pull downs. ? pxie:port x input control register to control inputs. for avoided through current, default setting prohibits inputs.
page 8-4 8. input / output ports 8.1 port functions TMPM372FWUG 2013/4/15 8.1.3 port states in stop mode input and output in stop mode are enable d / disabled by the cgstbycr bit. if pxie or pxcr is enabled with =1, input or output is enabled respectively in stop mode. if=0, both input and output are disabled in st op mode except for some por ts even if pxie or pxcr are enabled. table 8-2 shows the pin conditions in stop mode. table 8-2 port conditions in stop mode pin name i/o = 0 = 1 not port reset , mode input only port x1 input only x2 output only "high" level output tms tck tdi trst input tdo output enabled when data is valid. disabled when data is invalid. swclk input swdio input output enabled when data is valid. disabled when data is invalid. traceclk tracedata0 tracedata1 swv output uo1 vo1 wo1 xo1 yo1 zo1 output enabled when data is valid. disabled when data is invalid. int3, int4, int5 int6, int7, int8 intb intc, intd, inte intf input other function pins other than the above or the ports that are used as general purpose ports. input output : input or output enabled. : input or output disabled.
page 8-5 TMPM372FWUG 2013/4/15 8.2 port functions this chapter describes the port registers detail. this chapter describes only "circuit type" reading circuit configuration. for detailed circuit diagram, refer to"8.3 block diagrams of ports". 8.2.1 port a (pa0 to pa7) the port a is a general-purpose, 8-bit input / output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purp ose input / output functi on, the port a performs the serial interface func- tion (sio / uart), the external signal interrup t input, the 16-bit timer input/output function. reset initializes all bits of the port a as general- purpose ports with input, output, pull-up and pull-down dis- abled. the port a has two types of function register. if you us e the port a as a general-purpose port, set "0" to the corresponding bit of the two registers.if you use the port a as other than a general-purpose port, set "1" to the corresponding bit of the function register.do not set "1 " to the some function registers at the same time. to use the external interrupt input for releasing stop mode, select this function in the pafr and enable input in the paie register. these settings enable the interrupt input even if the cgstbycr bit in the clock / mode control block is set to stop driving of pins during stop mode. note:in modes other than stop mode, interrupt input is enabl ed regardless of the pxfr register setting if input is enabled in pxie. make sure to disable unused interrupts when programming the device. 8.2.1.1 port a circuit type 8.2.1.2 porta register 76543210 type t12 t11 t13 t9 t2 t12 t2 t12 base address = 0x4000_0000 register name address (base+) port a data register padata 0x0000 port a output control register pacr 0x0004 port a function register 1 pafr1 0x0008 port a function register2 pafr2 0x000c port a open drain control register paod 0x0028 port a pull-up control register papup 0x002c port a pull-down control register papdn 0x0030 port a input control register paie 0x0038
page 8-6 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.1.3 padata (port a data register) 8.2.1.4 pacr (port a output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pa6 pa5 pa4 pa3 pa2 pa1 pa0 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pa7 to pa0 r/w port a data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pa7c pa6c pa5c pa4c pa3c pa2c pa1c pa0c after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pa7c to pa0c r/w output 0: disable 1: enable
page 8-7 TMPM372FWUG 2013/4/15 8.2.1.5 pafr1 (port a function register 1) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pa7f1 pa6f1 pa5f1 pa4f1 pa3f1 pa2f1 pa1f1 pa0f1 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7 pa7f1 r/w 0 : port 1 : tb4in 6 pa6f1 r/w 0: port 1: rxd1 5 pa5f1 r/w 0: port 1: txd1 4 pa4f1 r/w 0: port 1: sclk1 3 pa3f1 r/w 0: port 1: tb1out 2 pa2f1 r/w 0: port 1: tb1in 1 pa1f1 r/w 0: port 1: tb0out 0 pa0f1 r/w 0: port 1: tb0in
page 8-8 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.1.6 pafr2 (port a function register 2) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pa7f2 pa6f2 pa5f2 pa4f2 - pa2f2 - pa0f2 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7 pa7f2 r/w 0 : port 1 : int8 6 pa6f2 r/w 0: port 1: tb6in 5 pa5f2 r/w 0: port 1: tb6out 4 pa4f2 r/w 0: port 1: cts1 3 ? r read as 0. 2 pa2f2 r/w 0: port 1: int4 1 ? r read as 0. 0 pa0f2 r/w 0: port 1: int3
page 8-9 TMPM372FWUG 2013/4/15 8.2.1.7 paod (port a open drain control register) 8.2.1.8 papup (port a pull-up control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pa7od pa6od pa5od pa4od pa3od pa2od pa1od pa0od after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pa7od to pa0od r/w 0 : cmos 1 : open-drain 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pa7up pa6up pa5up pa4up pa3up pa2up pa1up pa0up after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pa7up to pa0up r/w pull-up 0: disable 1: enable
page 8-10 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.1.9 papdn (port a pull-down control register) 8.2.1.10 paie (port a input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pa7dn pa6dn pa5dn pa4dn pa3dn pa2dn pa1dn pa0dn after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pa7dn to pa0dn r/w pull-down 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pa7ie pa6ie pa5ie pa4ie pa3ie pa2ie pa1ie pa0ie after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pa7ie to pa0ie r/w input 0: disable 1: enable
page 8-11 TMPM372FWUG 2013/4/15 8.2.2 port b (pb0 to pb7) the port b is a general-purpose, 8-bit input / output port.for this port, inputs and outputs can be specified in units of bits. besides the general-pu rpose input / output function, the port b performs the debug interface func- tion and the debug tr ace output function. reset initializes pb3, pb4, pb5, pb6 an d pb7 to perform debug interface function. when pb3 functions as the tms or swdio, input, ou tput and pull-up are enable d. when pb4 functions as the tck or swclk, input, pull-down are enabled. when pb5 functions as the tdo or swv, output is enabled. when pb6 functions tdi, input, pull-up are enabled. when pb7 functions as trst input, pull-up is enabled. pb0, pb1, pb2 perform as the general-purpose port s with input, output, pull-up, pull-down disabled. note:if pb3 is configured as the tms/swdio pin, output is enabled even in stop mode regardless of the cgst- bycr bit setting. 8.2.2.1 port b circuit type 8.2.2.2 port b register 76543210 type t7 t7 t19 t8 t6 t18 t18 t18 base address = 0x4000_0040 register name address(base+) port b data register pbdata 0x0000 port b output control register pbcr 0x0004 port b function register 1 pbfr1 0x0008 port b open drain control register pbod 0x0028 port b pull-up control register pbpup 0x002c port b pull-down control register pbpdn 0x0030 port b input control register pbie 0x0038
page 8-12 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.2.3 pbdata (port b data register) 8.2.2.4 pbcr (port b output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pb7 to pb0 r/w port b data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pb7c pb6c pb5c pb4c pb3c pb2c pb1c pb0c after reset00101000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pb7c to pb0c r/w output 0: disable 1: enable
page 8-13 TMPM372FWUG 2013/4/15 8.2.2.5 pbfr1 (port b function register 1) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pb7f1 pb6f1 pb5f1 pb4f1 pb3f1 pb2f1 pb1f1 pb0f1 after reset11111000 bit bit symbol type function 31-8 ? r read as 0. 7pb7f1 r/w0 : port 1 : trst 6pb6f1 r/w0: port 1: tdi 5pb5f1 r/w0: port 1: tdo / swv 4pb4f1 r/w0: port 1: tck / swclk 3pb3f1 r/w0: port 1: tms / swdio 2pb2f1 r/w0: port 1: tracedata1 1pb1f1 r/w0: port 1: tracedata0 0pb0f1 r/w0: port 1: traceclk
page 8-14 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.2.6 pbod (port b open drain control register) 8.2.2.7 pbpup (port b pull-up control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pb7od pb6od pb5od pb4od pb3od pb2od pb1od pb0od after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pb7od to pb0od r/w 0 : cmos 1 : open-drain 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pb7up pb6up pb5up pb4up pb3up pb2up pb1up pb0up after reset11001000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pb7up to pb0up r/w pull-up 0: disable 1: enable
page 8-15 TMPM372FWUG 2013/4/15 8.2.2.8 pbpdn (port b pull-down control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pb7dn pb6dn pb5dn pb4dn pb3dn pb2dn pb1dn pb0dn after reset00010000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pb7dn to pbdn r/w pull-down 0: disable 1: enable
page 8-16 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.2.9 pbie (port b input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pb7ie pb6ie pb5ie pb4ie pb3ie pb2ie pb1ie pb0ie after reset11011000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pb7ie to pb0ie r/w input 0: disable 1: enable
page 8-17 TMPM372FWUG 2013/4/15 8.2.3 port d (pd4 to pd6) the port d is a general-purpose, 3-bit input / output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purp ose input / output functi on, the port d performs the serial interface func- tion (sio / uart), the 16-bit timer input/ output function and the encoder input function. reset initializes all bits of the port d as general- purpose ports with input, output, pull-up and pull-down dis- abled. the port d has two types of function register. if you us e the port d as a general-purpose port, set "0" to the corresponding bit of the two registers.if you use the port d as other than a general-purpose port, set "1" to the corresponding bit of the function register.do not set "1 " to the some function registers at the same time. 8.2.3.1 port d circuit type 8.2.3.2 port d register 76543210 type - t3 t2 t9 - - - base address = 0x4000_00c0 register name address(base+) port d data register pddata 0x0000 port d output control register pdcr 0x0004 port d function register 1 pdfr1 0x0008 port d function register 2 pdfr2 0x000c port d open drain control register pdod 0x0028 port d pull-up control register pdpup 0x002c port d pull-down control register pdpdn 0x0030 port d input control register pdie 0x0038
page 8-18 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.3.3 pddata (port d data register) 8.2.3.4 pdcr (port d output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-pd6pd5pd4---- after reset00000000 bit bit symbol type function 31-7 ? r read as 0. 6-4 pd6 to pd4 r/w port d data register 3-0 ? r/w write "0". 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-pd6cpd5cpd4c---- after reset00000000 bit bit symbol type function 31-7 ? r read as 0. 6-4 pd6c to pd4c r/w output 0: disable 1: enable 3-0 ? r/w write "0".
page 8-19 TMPM372FWUG 2013/4/15 8.2.3.5 pdfr1 (port d function register 1) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-pd6f1pd5f1pd4f1---- after reset00000000 bit bit symbol type function 31-7 ? r read as 0. 6 pd6f1 r/w 0: port 1:rxd2 5 pd5f1 r/w 0: port 1: txd2 4 pd4f1 r/w 0: port 1: sclk2 3-0 ? r/w read as 0.
page 8-20 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.3.6 pdfr2 (port d function register 2) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-------- after reset00000000 bit bit symbol type function 31-5 ? r read as 0. 4 ? r/w write "0". 3-0 ? r read as 0.
page 8-21 TMPM372FWUG 2013/4/15 8.2.3.7 pdod (port d open drain control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-pd6odpd5odpd4od---- after reset00000000 bit bit symbol type function 31-7 ? r read as 0. 6-4 pd6od to pd4od r/w 0 : cmos 1 : open-drain 3-0 ? r read as 0.
page 8-22 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.3.8 pdpup (port d pull-up control register) 8.2.3.9 pdpdn (port d pull-down control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-pd6uppd5uppd4up---- after reset00000000 bit bit symbol type function 31-7 ? r read as 0. 6-4 pd6up to pdup r/w pull-up 0: disable 1: enable 3-0 ? r read as 0. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-pd6dnpd5dnpd4dn---- after reset00000000 bit bit symbol type function 31-7 ? r read as 0. 6-4 pd6dn to pd4dn r/w pull-down 0: disable 1: enable 3-0 ? r read as 0.
page 8-23 TMPM372FWUG 2013/4/15 8.2.3.10 pdie (port d input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-pd6iepd5iepd4ie---- after reset00000000 bit bit symbol type function 31-7 ? r read as 0. 6-4 pd6ie to pd4ie r/w input 0: disable 1: enable 3-0 ? r read as 0.
page 8-24 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.4 port e (pe0 to pe7) the port e is a general-purpose, 8-bit input / output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose input / output function, the port e performs the serial interface func- tion (sio / uart), the external signal interrupt input and the 16-bit timer input/output function. reset initializes all bits of the port e as general-purpose ports with input, output, pull-up and pull-down dis- abled. the port e has two types of function register. if you use the port e as a general-purpose port, set "0" to the corresponding bit of the two registers.if you use the port e as other than a general-purpose port, set "1" to the corresponding bit of the function register.do not set "1 " to the some function registers at the same time. to use the external interrupt input for releasing stop mode, select th is function in the pefr2 and enable input in the peie register. these settings enable the interrupt input even if the cgstbycr bit in the clock / mode control block is set to stop driving of pins during stop mode. note:in modes other than stop mode, interrupt input is enabl ed regardless of the pxfr register setting if input is enabled in pxie. make sure to disable unused interrupts when programming the device. 8.2.4.1 port e circuit type 8.2.4.2 port e register 76543210 type t14 t12 t2 t12 t2 t9 t3 t2 base address = 0x4000_0100 register name address(base+) port e data register pedata 0x0000 port e output control register pecr 0x0004 port e function register 1 pefr1 0x0008 port e function register 2 pefr2 0x000c port e open drain control register peod 0x0028 port e pull-up control register pepup 0x002c port e pull-down control register pepdn 0x0030 port e input control register peie 0x0038
page 8-25 TMPM372FWUG 2013/4/15 8.2.4.3 pedata (port e data register) 8.2.4.4 pecr (port e output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pe7 pe6 pe2 pe1 pe0 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pe7 to pe0 r/w port e data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pe7c pe6c pe5c pe4c pe3c pe2c pe1c pe0c after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pe7c to pe0c r/w output 0: disable 1: enable
page 8-26 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.4.5 pefr1 (port e function register 1) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pe7f1 pe6f1 pe5f1 pe4f1 pe3f1 pe2f1 pe1f1 pe0f1 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7pe7f1 r/w0: port 1:tb3out 6pe6f1 r/w0: port 1:tb3in 5pe5f1 r/w0: port 1: tb2out 4pe4f1 r/w0: port 1: tb2in 3pe3f1 r/w0: port 1: tb4out 2pe2f1 r/w0: port 1: sclk0 1pe1f1 r/w0: port 1: rxd0 0pe0f1 r/w0: port 1: txd0
page 8-27 TMPM372FWUG 2013/4/15 8.2.4.6 pefr2 (port e function register 2) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pe7f2 pe6f2 - pe4f2 - pe2f2 - - after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7pe7f2 r/w0 : port 1 : int7 6pe6f2 r/w0: port 1: int6 5 ? r read as 0. 4pe4f2 r/w0: port 1: int5 3 ? r read as 0. 2pe2f2 r/w0: port 1: cts0 1-0 ? r read as 0.
page 8-28 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.4.7 peod (port e open drain control register) 8.2.4.8 pepup (port e pull-up control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pe7od pe6od pe5od pe4od pe3od pe2od pe1od pe0od after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pe7od to pe0od r/w 0 : cmos 1 : open-drain 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pe7up pe6up pe5up pe4up pe3up pe2up pe1up pe0up after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pe7up to pe0up r/w pull-up 0: disable 1: enable
page 8-29 TMPM372FWUG 2013/4/15 8.2.4.9 pepdn (port e pull-down control register) 8.2.4.10 peie (port e input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pe7dn pe6dn pe5dn pe4dn pe3dn pe2dn pe1dn pe0dn after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pe7dn to pe0dn r/w pull-down 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pe7ie pe6ie pe5ie pe4ie pe3ie pe2ie pe1ie pe0ie after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pe7ie to pe0ie r/w input 0: disable 1: enable
page 8-30 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.5 port f (pf0 to pf4) the port f is a general-purpose, 5-bit input / output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purp ose input / output function, the port f performs the serial interface func- tion (sio / uart), the 16-bit timer input/output function, the encoder input function and the operation mode setting. while a reset signal is in "0"state, the pf0 input and pull-up are enabled. at the rising edge of the reset sig- nal, if pf0 is "1", the device enters single mode and boots from the on-chip flash memory. if pf0 is "0", the device enters single boot mode and boots from the internal boot program. for details of single boot mode, refer to chapter "flash memory operation". reset initializes all bits of the port f as general-pur pose ports with input, output, pull-up and pull-down dis- abled. 8.2.5.1 port f circuit type 8.2.5.2 port f register 76543210 type ??? t11 t10 t15 t2 t20 base address = 0x4000_0140 register name address(base+) port f data register pfdata 0x0000 port f output control register pfcr 0x0004 port f function register 1 pffr1 0x0008 port f function register 2 pffr2 0x000c port f function register 3 pffr3 0x0010 port f open drain control register pfod 0x0028 port f pull-up control register pfpup 0x002c port f pull-down control register pfpdn 0x0030 port f input control register pfie 0x0038
page 8-31 TMPM372FWUG 2013/4/15 8.2.5.3 pfdata (port f data register) 8.2.5.4 pfcr (port f output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - pf4 pf3 pf2 pf1 pf0 after reset00000000 bit bit symbol type function 31-5 ? r read as 0. 4-0 pf4 to pf0 r/w port f data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - pf4c pf3c pf2c pf1c pf0c after reset00000000 bit bit symbol type function 31-5 ? r read as 0. 4-0 pf4c to pf0c r/w output 0: disable 1: enable
page 8-32 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.5.5 pffr1 (port f function register 1) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - pf4f1 pf3f1 pf2f1 pf1f1 pf0f1 after reset00000000 bit bit symbol type function 31-5 ? r read as 0. 4 pf4f1 r/w 0: port 1: encz1 3 pf3f1 r/w 0: port 1: encb1 2 pf2f1 r/w 0: port 1: enca1 1 pf1f1 r/w 0: port 1: tb7out 0 pf0f1 r/w 0: port 1: tb7in
page 8-33 TMPM372FWUG 2013/4/15 8.2.5.6 pffr2 (port f function register 2) 8.2.5.7 pffr3 (port f function register 3) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - pf4f2 pf3f2 pf2f2 - - after reset00000000 bit bit symbol type function 31-5 ? r read as 0. 4 pf4f2 r/w 0: port 1: rxd3 3 pf3f2 r/w 0: port 1: txd3 2 pf2f2 r/w 0: port 1: sclk3 1-0 ? r read as 0. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-----pf2f3-- after reset00000000 bit bit symbol type function 31-3 ? r read as 0. 2 pf2f3 r/w 0: port 1: cts3 1-0 ? r read as 0.
page 8-34 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.5.8 pfod (port f open drain control register) 8.2.5.9 pfpup (port f pull-up control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - pf4od pf3od pf2od pf1od pf0od after reset00000000 bit bit symbol type function 31-5 ? r read as 0. 4-0 pf4od to pf0od r/w 0 : cmos 1 : open-drain 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - pf4up pf3up pf2up pf1up pf0up after reset00000000 bit bit symbol type function 31-5 ? r read as 0. 4-0 pf4up to pf0up r/w pull-up 0: disable 1: enable
page 8-35 TMPM372FWUG 2013/4/15 8.2.5.10 pfpdn (port f pull-down control register) 8.2.5.11 pfie (port f input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - pf4dn pf3dn pf2dn pf1dn pf0dn after reset00000000 bit bit symbol type function 31-5 ? r read as 0. 4-0 pf4dn to pf0dn r/w pull-down 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - pf4ie pf3ie pf2ie pf1ie pf0ie after reset00000000 bit bit symbol type function 31-5 ? r read as 0. 4-0 pf4ie to pf0ie r/w input 0: disable 1: enable
page 8-36 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.6 port g (pg0 to pg7) the port g is a general-purpose, 8-bit input / output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose input / output function, the port g performs the input/output port for three-phase motor control (pmd) function. reset initializes all bits of the port g as general- purpose ports with input, output, pull-up and pull-down dis- abled. 8.2.6.1 port g circuit type 8.2.6.2 port g register 76543210 type t3 t3 t1 t1 t1 t1 t1 t1 base address = 0x4000_0180 register name address(base+) port g data register pgdata 0x0000 port g output control register pgcr 0x0004 port g function register 1 pgfr1 0x0008 port g open drain control register pgod 0x0028 port g pull-up control register pgpup 0x002c port g pull-down control register pgpdn 0x0030 port g input control register pgie 0x0038
page 8-37 TMPM372FWUG 2013/4/15 8.2.6.3 pgdata (port g data register) 8.2.6.4 pgcr (port g output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbolpg7pg6pg5pg4pg3pg2pg1pg0 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pg7 to pg0 r/w port g data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pg7c pg6c pg5c pg4c pg3c pg2c pg1c pg0c after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pg7c to pg0c r/w output 0: disable 1: enable
page 8-38 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.6.5 pgfr1 (port g function register 1) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pg7f1 pg6f1 pg5f1 pg4f1 pg3f1 pg2f1 pg1f1 pg0f1 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7 pg7f1 r/w 0: port 1: ovv1 6 pg6f1 r/w 0: port 1: emg1 5 pg5f1 r/w 0: port 1: zo1 4 pg4f1 r/w 0: port 1: wo1 3 pg3f1 r/w 0: port 1: yo1 2 pg2f1 r/w 0: port 1: vo1 1 pg1f1 r/w 0: port 1: xo1 0 pg0f1 r/w 0: port 1: uo1
page 8-39 TMPM372FWUG 2013/4/15 8.2.6.6 pgod (port g open drain control register) 8.2.6.7 pgpup (port g pull-up control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pg7od pg6od pg5od pg4od pg3od pg2od pg1od pg0od after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pg7od to pg0od r/w 0 : cmos 1 : open-drain 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pg7up pg6up pg5up pg4up pg3up pg2up pg1up pg0up after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pg7up to pg0up r/w pull-up 0: disable 1: enable
page 8-40 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.6.8 pgpdn (port g pull-down control register) 8.2.6.9 pgie (port g input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pg7dn pg6dn pg5dn pg4dn pg3dn pg2dn pg1dn pg0dn after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pg7dn to pg0dn r/w pull-down 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pg7ie pg6ie pg5ie pg4ie pg3ie pg2ie pg1ie pg0ie after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pg7ie to pg0ie r/w input 0: disable 1: enable
page 8-41 TMPM372FWUG 2013/4/15 8.2.7 port i (pi3) the port i is a general-purpose, 1-bit input / output port. for this port, in puts and outputs can be specified in units of bits. besides the general-purpose input / output function, the port i performs the analog input of the ad converter. reset initializes all bits of the port i as general- purpose ports with input, output, pull-up and pull-down dis- abled. note:unless you use all the bits of port i as analog input pins, conversion accuracy may be reduced.be sure to ver- ify that this causes no problem on your system. 8.2.7.1 port i circuit type 8.2.7.2 port i register 76543210 type ???? t16 - - - base address = 0x4000_0200 register name address(base+) port i data register pidata 0x0000 port i output control register picr 0x0004 port i open drain control register piod 0x0028 port i pull-up control register pipup 0x002c port i pull-down control register pipdn 0x0030 port i input control register piie 0x0038
page 8-42 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.7.3 pidata (port i data register) 8.2.7.4 picr (port i output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol----pi3--- after reset00000000 bit bit symbol type function 31-4 ? r read as 0. 3 pi3 r/w port i data register 2-0 ? r/w read as 0. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol----pi3cpi2c-pi1c-pi0c- after reset00000000 bit bit symbol type function 31-4 ? r read as 0. 3 pi3c r/w output 0: disable 1: enable 2-0 ? r/w read as 0.
page 8-43 TMPM372FWUG 2013/4/15 8.2.7.5 piod (port i open drain control register) 8.2.7.6 pipup (port i pull-up control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol----pi3od--- after reset00000000 bit bit symbol type function 31-4 ? r read as 0. 3 pi3od r/w 0 : cmos 1 : open-drain 2-0 ? r/w read as 0. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol----pi3up--- after reset00000000 bit bit symbol type function 31-4 ? r read as 0. 3 pi3up r/w pull-up 0: disable 1: enable 2-0 ? r/w read as 0.
page 8-44 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.7.7 pipdn (port i pull-down control register) 8.2.7.8 piie (port i input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol----pi3dn--- after reset00000000 bit bit symbol type function 31-4 ? r read as 0. 3 pi3dn r/w pull-down 0: disable 1: enable 2-0 ? r/w read as 0. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol----pi3ie--- after reset00000000 bit bit symbol type function 31-4 ? r read as 0. 3 pi3ie r/w input 0: disable 1: enable 2-0 ? r/w read as 0.
page 8-45 TMPM372FWUG 2013/4/15 8.2.8 port j (pj0 to pj7) the port j is a general-purpose, 8-bit input / output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose input / output function, the port j perfor ms the analog input of the ad converterand the external signal interrupt input. reset initializes all bits of the port j as general- purpose ports with input, output, pull-up and pull-down dis- abled. to use the external interrupt input for releasing stop mode, select this function in the pjfr1 and enable input in the pjie register. these settings enable the interrupt input even if the cgstbycr bit in the clock / mode control block is set to stop driving of pins during stop mode. note 1: unless you use all the bits of port j as analog input pins, conversion accuracy may be reduced.be sure to verify that this causes no problem on your system. note 2: in modes other than stop mode, interrupt input is enabled regardless of the pxfr register setting if input is enabled in pxie. make sure to disabl e unused interrupts when programming the device. 8.2.8.1 port j circuit type 8.2.8.2 port j register 76543210 type t17 t17 t16 t16 t16 t16 t16 t16 base address = 0x4000_0240 register name address(base+) port j data register pjdata 0x0000 port j output control register pjcr 0x0004 port j function register 1 pjfr1 0x0008 port j open drain control register pjod 0x0028 port j pull-up control register pjpup 0x002c port j pull-down control register pjpdn 0x0030 port j input control register pjie 0x0038
page 8-46 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.8.3 pjdata (port j data register) 8.2.8.4 pjcr (port j output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pj7 pj6 pj5 pj4 pj3 pj2 pj1- pj0 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pj7 to pj0 r/w port j data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pj7c pj6c pj5c pj4c pj3c pj2c pj1c pj0c a f t e r r e s e t00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pj7c to pj0c r/w output 0: disable 1: enable
page 8-47 TMPM372FWUG 2013/4/15 8.2.8.5 pjfr1 (port j function register 1) 8.2.8.6 pjod (port j open drain control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbolpj7f1pj6f1------ after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7pj7f1 r/w0: port 1: intd 6pj6f1 r/w0: port 1: intc 5-0 ? r read as 0. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pj7od pj6od pj5od pj4od pj3od pj2od pj1od pj0od after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pj7od to pj0od r/w 0 : cmos 1 : open-drain
page 8-48 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.8.7 pjpup (port j pull-up control register) 8.2.8.8 pjpdn (port j pull-down control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pj7up pj6up pj5up pj4up pj3up pj2up pj1up pj0up after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pj7up to pj0up r/w pull-up 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pj7dn pj6dn pj5dn pj4dn pj3dn pj2dn pj1dn pj0dn after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pj7dn-pj0dn r/w pull-down 0: disable 1: enable
page 8-49 TMPM372FWUG 2013/4/15 8.2.8.9 pjie (port j input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pj7ie pj6ie pj5ie pj4ie pj3ie pj2ie pj1ie pj0ie after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pj7ie to pj0ie r/w input 0: disable 1: enable
page 8-50 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.9 port k (pk0 to pk1) the port k is a general-purpose, 2-bit input / output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose input / output function, the port k performs the analog input of the ad converter and the external signal interrupt input. reset initializes all bits of the port k as general- purpose ports with input, output, pull-up and pull-down dis- abled. to use the external interrupt input for releasing stop mode, select this function in the pkfr1 and enable input in the pkie register. these settings enable the interrupt input even if the cgstbycr bit in the clock / mode control block is set to stop driving of pins during stop mode. note 1: unless you use all the bits of port k as analog input pins, conversion accura cy may be reduced.be sure to verify that this causes no problem on your system. note 2: in modes other than stop mode, interrupt input is enabled regardless of the pxfr register setting if input is enabled in pxie. make sure to disabl e unused interrupts when programming the device. 8.2.9.1 port k circuit type 8.2.9.2 port k register 76543210 t y p e ------t 1 7t 1 7 base address = 0x4000_0280 register name address(base+) port k data register pkdata 0x0000 port k output control register pkcr 0x0004 port k function register 1 pkfr1 0x0008 port k open drain control register pkod 0x0028 port k pull-up control register pkpup 0x002c port k pull-down control register pkpdn 0x0030 port k input control register pkie 0x0038
page 8-51 TMPM372FWUG 2013/4/15 8.2.9.3 pkdata (port k data register) 8.2.9.4 pkcr (port k output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pk1pk0 after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pk1 to pk0 r/w port k data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - pk1c pk0c after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pk1c to pk0c r/w output 0: disable 1: enable
page 8-52 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.9.5 pkfr1 (port k function register 1) 8.2.9.6 pkod (port k open drain control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pk1f1pk0f1 after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1pk1f1 r/w0: port 1: intf 0pk0f1 r/w0: port 1: inte 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pk1odpk0od after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pk1od to pk0od r/w 0 : cmos 1 : open-drain
page 8-53 TMPM372FWUG 2013/4/15 8.2.9.7 pkpup (port k pull-up control register) 8.2.9.8 pkpdn (port k pull-down control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pk1uppk0up after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pk1up to pk0up r/w pull-up 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pk1dnpk0dn after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pk1dn- pk0dn r/w pull-down 0: disable 1: enable
page 8-54 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.9.9 pkie (port k input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pk1iepk0ie after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pk1ie-pk0ie r/w input 0: disable 1: enable
page 8-55 TMPM372FWUG 2013/4/15 8.2.10 port m (pm0 to pm1) the port m is a general-purpose, 2-bit input/output port . for this port, inputs and outputs can be specified in units of bits. besides the general-purpose input/o utput function, the port m performs the high-speed oscillator1(x1 and x2) by cgosccr=1. while it become cgosccr=1, each register of port m can not change to write. the procedure when it is used as an outside high-speed oscillator connection terminal look at a chapter of the "system clock".(note1) reset initializes all bits of the port m as general-purp ose ports with input, output, pull-up and pull-down dis- abled.(note2) note 1: if one of the port m registers except pmdata and pmod is not equal to the initial value, cgosccr can not be set to "1". note 2: the high-speed clock chosen after reset cancellation is a built-in high-s peed clock. therefore, in the initial state, it become port m. 8.2.10.1 port m circuit type 8.2.10.2 port m register 76543210 t y p e ------t 2 1t 2 1 base address = 0x4000_0300 register name address(base+) port m data register pmdata 0x0000 port m output control register pmcr 0x0004 port m open drain control register pmod 0x0028 port m pull-up control register pmpup 0x002c port m pull-down control register pmpdn 0x0030 port m input control register pmie 0x0038
page 8-56 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.10.3 pmdata (port m data register) 8.2.10.4 pmcr (port m output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pm1pm0 after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pm1 to pm0 r/w port m data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pm1cpm0c after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pm1c to pm0c r/w output 0: disable 1: enable
page 8-57 TMPM372FWUG 2013/4/15 8.2.10.5 pmod (port m open drain control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pm1odpm0od after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pm1od to pm0od r/w 0 : cmos 1 : open-drain
page 8-58 8. input / output ports 8.2 port functions TMPM372FWUG 2013/4/15 8.2.10.6 pmpup (port m pull-up control register) 8.2.10.7 pmpdn (port m pull-down control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pm1uppm0up after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pm1up to pm0up r/w pull-up 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pm1dnpm0dn after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pm1dn to pm0dn r/w pull-down 0: disable 1: enable
page 8-59 TMPM372FWUG 2013/4/15 8.2.10.8 pmie (port m input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pm1iepm0ie after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pm1ie to pm0ie r/w input 0: disable 1: enable
page 8-60 8. input / output ports 8.3 block diagrams of ports TMPM372FWUG 2013/4/15 8.3 block diagra ms of ports 8.3.1 port types the ports are classified as shown below. please refer to the following pages for the block diagrams of each port type. dot lines in the figure indicate the part of the equivale nt circuit described in the "block diagrams of ports". table 8-3 function lists type gp port function1 function2 function3 analog pull-up pull-dn program- mable open-drain note t1 i / o output ??? rr function output triggered by enable signal t2 i / o output ??? rr t3 i / o input ??? rr t4 i / o input (int) ??? rr t5 input input (int) ?????? t6 i / o i / o ??? nor ?? function output triggered by enable signal t7 i / o input ??? nor ?? t8 i / o input ???? nor ? t9 i / o i / o input ?? rr t10 i / o input output ?? rr t11 i / o input input ?? rr t12 i / o input input(int) ?? rr t13 i / o output output ?? rr t14 i / o output i / o ?? rr t15 i / o input i / o input ? rr t16 i / o ??? rr t17 i / o input(int) ?? rr t18 i / o output ??? r ?? t19 i / o output ??? nor ?? function output triggered by enable signal t20 i / o input ??? nor nor boot input enabled during reset t21 i / o - (osc1) ??? rr high-speed osscillator (external) int : interrupt input - : not exist o : exist r: forced disable during reset nor: unaffected by reset
page 8-61 TMPM372FWUG 2013/4/15 8.3.2 type t1 figure 8-1 port type t1 pxpup (pull-up control) i /o port port read 0 1 1 0 reset drive disable in stop mode (set by ) pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) function output 0 1 function output enable internal data bus programable pull-up and pull-down
page 8-62 8. input / output ports 8.3 block diagrams of ports TMPM372FWUG 2013/4/15 8.3.3 type t2 figure 8-2 port type t2 pxpup (pull-up control) port read 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output controll) pxpdn (pull-down control) function output 0 1 internal data bus i /o port programable pull-up and pull-down drive disable in stop mode (set by )
page 8-63 TMPM372FWUG 2013/4/15 8.3.4 type t3 figure 8-3 port type t3 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output controll) pxpdn (pull-down control) port read i /o port programable pull-up and pull-down drive disable in stop mode (set by ) internal data bus function input1
page 8-64 8. input / output ports 8.3 block diagrams of ports TMPM372FWUG 2013/4/15 8.3.5 type t4 figure 8-4 port type t4 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output controll) pxpdn (pull-down control) +pvgttwrv +prwv internal data bus port read i /o port drive disable in stop mode (set by ) programable pull-up and pull-down
page 8-65 TMPM372FWUG 2013/4/15 8.3.6 type t5 figure 8-5 port type t5 0 1 pxie (input control) pxfr1 (function control) ,qwhuuxsw ,qsxw i /o port drive disable in stop mode (set by ) internal data bus port read
page 8-66 8. input / output ports 8.3 block diagrams of ports TMPM372FWUG 2013/4/15 8.3.7 type t6 figure 8-6 port type t6 pxpup (pull-up control) 0 1 1 0 pxie (input control) pxdata (output latch) pxfr1 (function control) pxcr (output controll) 0 1 1 0 (wpevkqp +prwv port read function output function output enable i /o port drive disable in stop mode (set by ) programable pull-up internal data bus
page 8-67 TMPM372FWUG 2013/4/15 8.3.8 type t7 figure 8-7 port type t7 pxpup (pull-up control) 0 1 pxie (input control) pxdata (output latch) pxfr1 (?(??) pxcr (output control) 1 0 reset (wpevkqp +prwv port read i /o port drive disable in stop mode (set by ) programable pull-up internal data bus
page 8-68 8. input / output ports 8.3 block diagrams of ports TMPM372FWUG 2013/4/15 8.3.9 type t8 figure 8-8 port type t8 0 1 pxie (input control) pxdata (output latch) pxfr1 (?(??) pxcr (output control) 1 0 (wpevkqp +prwv reset pxpdn (pull-down control) internal data bus port read i /o port drive disable in stop mode (set by ) programable pull-down
page 8-69 TMPM372FWUG 2013/4/15 8.3.10 type t9 figure 8-9 port type t9 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) 0 1 (wpevkqp +prwv pxfr2 (function control (wpevkqp input2 i /o port drive disable in stop mode (set by ) programable pull-up and pull-down internal data bus function output port read
page 8-70 8. input / output ports 8.3 block diagrams of ports TMPM372FWUG 2013/4/15 8.3.11 type t10 figure 8-10 port type t10 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) 0 1 (wpevkqp +prwv1 pxfr2 (function control) i /o port drive disable in stop mode (set by ) programable pull-up and pull-down internal data bus port read function output
page 8-71 TMPM372FWUG 2013/4/15 8.3.12 type t11 figure 8-11 port type t11 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) (wpevkqp +prwv1 pxfr2 (function control) (wpevkqp input2 internal data bus port read i /o port drive disable in stop mode (set by ) programable pull-up and pull-down
page 8-72 8. input / output ports 8.3 block diagrams of ports TMPM372FWUG 2013/4/15 8.3.13 type t12 figure 8-12 port type t12 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) (wpevkqp input1 pxfr2 (function control) +pvgttwrv +prwv i /o port drive disable in stop mode (set by ) programable pull-up and pull-down port read internal data bus
page 8-73 TMPM372FWUG 2013/4/15 8.3.14 type t13 figure 8-13 port type t13 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) 0 1 pxfr2 (function control) 0 1 internal data bus function output1 function output2 port read i /o port drive disable in stop mode (set by ) programable pull-up and pull-down
page 8-74 8. input / output ports 8.3 block diagrams of ports TMPM372FWUG 2013/4/15 8.3.15 type t14 figure 8-14 port type t14 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) pxfr2 (function control) +pvgttwrv +prwv 0 1 internal data bus function output port read i /o port drive disable in stop mode (set by ) programable pull-up and pull-down
page 8-75 TMPM372FWUG 2013/4/15 8.3.16 type t15 figure 8-15 port type t15 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain contro) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) 0 1 (wpevkqp+prwv1 pxfr2 (function control) pxfr3 (function control) (wpevkqp+prwv2 (wpevkqp+prwv3 i /o port drive disable in stop mode (set by ) programable pull-up and pull-down internal data bus function output2 port read
page 8-76 8. input / output ports 8.3 block diagrams of ports TMPM372FWUG 2013/4/15 8.3.17 type t16 figure 8-16 port type t16 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxcr (output control) pxpdn (pull-down control) analog input internal data bus port read i /o port drive disable in stop mode (set by ) programable pull-up and pull-down
page 8-77 TMPM372FWUG 2013/4/15 8.3.18 type t17 figure 8-17 port type t17 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) interrupt input analog input i /o port drive disable in stop mode (set by ) programable pull-up and pull-down internal data bus port read
page 8-78 8. input / output ports 8.3 block diagrams of ports TMPM372FWUG 2013/4/15 8.3.19 type t18 figure 8-18 port type t18 pxpup (pull-up control) 0 1 1 0 pxie (input control) pxdata (output latch) pxfr1 (function control) pxcr (output control) 0 1 reset port read internal data bus function output1 i /o port drive disable in stop mode (set by ) programable pull-up and pull-down
page 8-79 TMPM372FWUG 2013/4/15 8.3.20 type t19 figure 8-19 port type t19 pxpup (pull-up control) 1 0 pxie (input control) pxdata (output latch) pxfr1 (function control) pxcr (output control) 0 1 0 1 i /o port drive disable in stop mode (set by ) programable pull-up and pull-down port read internal data bus function output function output enable
page 8-80 8. input / output ports 8.3 block diagrams of ports TMPM372FWUG 2013/4/15 8.3.21 type t20 pxpup (pull-up control) 0 1 reset pxie (input control)) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) (wpevkqp +prwv1 boot port read internal data bus i /o port drive disable in stop mode (set by ) programable pull-up and pull-down
page 8-81 TMPM372FWUG 2013/4/15 8.3.22 type t21 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxcr (output control) pxpdn (pull-down control) external high-speed oscillator port read internal data bus i /o port drive disable in stop mode (set by ) programable pull-up and pull-down
page 8-82 8. input / output ports 8.4 appendix port setting list TMPM372FWUG 2013/4/15 8.4 appendix port setting list the following table shows the re gister setting for each function. initialization of the ports where the [ ? ]does not exist in the "after reset" field is set to "0" for all register settings. setting for the bit "x" can be arbitrarily-specified. 8.4.1 port a setting table 8-4 port setting list(port a) pin port type function after reset pacr pafr1 pafr2 paod papup papdn paie pa0 t12 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 tb0in (input) 0 1 0 x x x 1 int7 (input) 0 0 1 x x x 1 pa1 t2 input port 0 0 - x x x 1 output port 1 0 - x x x 0 tb0out(output) 1 1 - x x x 0 pa2 t12 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 tb1in (input) 0 1 0 x x x 1 int4 (input) 0 0 1 x x x 1 pa3 t2 input port 0 0 - x x x 1 output port 1 0 - x x x 0 tb1out(output) 1 1 - x x x 0 pa4 t9 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 sclk1 (i / o) 110xxx1 cts1 (input) 0 0 1 x x x 1 pa5 t13 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 txd1 (output) 1 1 0 x x x 0 tb6out(output) 1 0 1 x x x 0 pa6 t11 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 rxd1 (input) 0 1 0 x x x 1 tb6in (input) 0 0 1 x x x 1 pa7 t12 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 tb4in (input) 0 1 0 x x x 1 int8 (input) 0 0 1 x x x 1
page 8-83 TMPM372FWUG 2013/4/15 8.4.2 port b setting table 8-5 port setting list(port b) pin port type function after reset pbcr pbfr1 pbod pbpup pbpdn pbie pb0 t18 input port 0 0 x x x 1 output port 10xxx0 traceclk (output) 110000 pb1 t18 input port 0 0 x x x 1 output port 10xxx0 tracedata0 (output) 110000 pb2 t18 input port 0 0 x x x 1 output port 10xxx0 tracedata1 (output) 110000 pb3 t6 input port 0 0 x x x 1 output port 10xxx0 tms / swdio (i / o) 110101 pb4 t8 input port 0 0 x x x 1 output port 10xxx0 tck / swclk (input) 010011 pb5 t19 input port 0 0 x x x 1 output port 10xxx0 tdo / swv (output) 110000 pb6 t7 input port 0 0 x x x 1 output port 10xxx0 tdi (input) 010101 pb7 t7 input port 0 0 x x x 1 output port 10xxx0 trst (input) 0 1 0111
page 8-84 8. input / output ports 8.4 appendix port setting list TMPM372FWUG 2013/4/15 8.4.3 port d setting table 8-6 port setting list(port d) pin port type function after reset pdcr pdfr1 pdfr2 pdod pdpup pdpdn pdie pd4 t9 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 sclk2 (i / o) 110xxx1 cts2 (input) 0 0 1 x x x 1 pd5 t2 input port 0 0 - x x x 1 output port 1 0 - x x x 0 txd2 (output) 1 1 - x x x 0 pd6 t3 input port 0 0 - x x x 1 output port 1 0 - x x x 0 rxd2 (input) 0 1 - x x x 1
page 8-85 TMPM372FWUG 2013/4/15 8.4.4 port e setting table 8-7 port setting list(port e) pin port type function after reset pecr pefr1 pefr2 peod pepup pepdn peie pe0 t2 input port 0 0 - x x x 1 output port 1 0 - x x x 0 txd0 (output) 1 1 - x x x 0 pe1 t3 input port 0 0 - x x x 1 output port 1 0 - x x x 0 rxd0 (input) 0 1 - x x x 1 pe2 t9 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 sclk0 (i / o) 110xxx1 cts0 (input) 0 0 1 x x x 1 pe3 t2 input port 0 0 - x x x 1 output port 1 0 - x x x 0 tb4out (output) 1 1 - x x x 0 pe4 t12 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 tb2in (input) 0 1 0 x x x 1 int5 (input) 0 0 1 x x x 1 pe5 t2 input port 0 0 - x x x 1 output port 1 0 - x x x 0 tb2out (output) 1 1 - x x x 0 pe6 t12 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 tb3in (input) 0 1 0 x x x 1 int6 (input) 0 0 1 x x x 1 pe7 t14 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 tb3out (output) 1 1 0 x x x 0 int7 (input) 0 0 1 x x x 1
page 8-86 8. input / output ports 8.4 appendix port setting list TMPM372FWUG 2013/4/15 8.4.5 port f setting note:the pf0 input and pull-up are enabled and act as boot input pin while a reset is in "low" state table 8-8 port setting list(port f) pin port type function after reset pfcr pffr1 pffr2 pffr3 pfod pfpup pfpdn pfie pf0 t20 input port 0 0 - - x x x 1 output port 1 0 - - x x x 0 tb7in (input) 0 1 - - x x x 1 pf1 t2 input port 0 0 - - x x x 1 output port 1 0 - - x x x 0 tb7out (output) 1 1 - - x x x 0 pf2 t15 input port 0 0 0 0 x x x 1 output port 1 0 0 0 x x x 0 enca1 (input) 0 1 0 0 x x x 1 sclk3 (i / o) 1 0 1 0 x x x 1 cts3 (input) 0 0 0 1 x x x 1 pf3 t10 input port 0 0 0 - x x x 1 output port 1 0 0 - x x x 0 encb1 (input) 0 1 0 - x x x 1 txd3 (output) 1 0 1 - x x x 0 pf4 t11 input port 0 0 0 - x x x 1 output port 1 0 0 - x x x 0 encz1 (input) 0 1 0 - x x x 1 rxd3 (input) 0 0 1 - x x x 1
page 8-87 TMPM372FWUG 2013/4/15 8.4.6 port g setting 8.4.7 port i setting table 8-9 port setting list(port g) pin port type function after reset pgcr pgfr1 pgod pgpup pgpdn pgie pg0 t1 input port 0 0 x x x 1 output port 10xxx0 uo1 (output) 1 1 x x x 0 pg1 t1 input port 0 0 x x x 1 output port 10xxx0 xo1 (output) 1 1 x x x 0 pg2 t1 input port 0 0 x x x 1 output port 10xxx0 vo1 (output) 1 1 x x x 0 pg3 t1 input port 0 0 x x x 1 output port 10xxx0 yo1 (output) 1 1 x x x 0 pg4 t1 input port 0 0 x x x 1 output port 10xxx0 wo1 (output) 1 1 x x x 0 pg5 t1 input port 0 0 x x x 1 output port 10xxx0 zo1 (output) 1 1 x x x 0 pg6 t3 input port 0 0 x x x 1 output port 10xxx0 emg1 (input) 0 1 x x x 1 pg7 t3 input port 0 0 x x x 1 output port 10xxx0 ovv1 (input) 0 1 x x x 1 table 8-10 port setting list(port i) pin port type function after reset picr piod pipup pipdn piie pi3 t16 input port 0xxx1 output port 1 x x x 0 analog input 00000
page 8-88 8. input / output ports 8.4 appendix port setting list TMPM372FWUG 2013/4/15 8.4.8 port j setting table 8-11 port setting list(port j) pin port type function after reset pjcr pjfr1 pjod pjpup pjpdn pjie pj0 t16 input port 0 - x x x 1 output port 1 - x x x 0 analog input 0 - 0000 pj1 t16 input port 0 - x x x 1 output port 1 - x x x 0 analog input 0 - 0000 pj2 t16 input port 0 - x x x 1 output port 1 - x x x 0 analog input 0 - 0000 pj3 t16 input port 0 - x x x 1 output port 1 - x x x 0 analog input 0 - 0000 pj4 t16 input port 0 - x x x 1 output port 1 - x x x 0 analog input 0 - 0000 pj5 t16 input port 0 - x x x 1 output port 1 - x x x 0 analog input 0 - 0000 pj6 t17 input port 0 0 x x x 1 output port 1 0 x x x 0 analog input 000000 intc (input) 0 1 x x x 1 pj7 t17 input port 0 0 x x x 1 output port 1 0 x x x 0 analog input 000000 intd (input) 0 1 x x x 1
page 8-89 TMPM372FWUG 2013/4/15 8.4.9 port k setting 8.4.10 port m setting note:x1,x2 exist table 8-12 port setting list(port k) pin port type function after reset pkcr pkfr1 pkod pkpup pkpdn pkie pk0 t17 input port 0 0 x x x 1 output port 10xxx0 analog input 0 0 0000 inte (input) 0 1 x x x 1 pk1 t17 input port 0 0 x x x 1 output port 10xxx0 analog input 0 0 0000 intf (input) 0 1 x x x 1 table 8-13 port setting list(port m) pin port type function after reset pmcr pmod pmpup pmpdn pmie pm0 t21 input port 0xxx1 output port 1 x x x 0 pm1 t21 input port 0xxx1 output port 1 x x x 0
page 8-90 8. input / output ports 8.4 appendix port setting list TMPM372FWUG 2013/4/15
page 9-1 TMPM372FWUG 2013/4/15 9. 16-bit timer / event counters (tmrb) 9.1 outline tmrb operate in the following four operation modes: ? 16-bit interval timer mode ? 16-bit event counter mode ? 16-bit programmable pulse generation mode (ppg) ? external trigger programmable pulse generation mode (ppg) the use of the capture function allows tmrb to perform the following two measurements. ? one shot pulse output by an external trigger ? pulse width measurement in the following explanation of this s ection, "x" indicates a channel number.
page 9-2 9. 16-bit timer / event counters (tmrb) 9.2 differences in the specifications TMPM372FWUG 2013/4/15 9.2 differences in the specifications TMPM372FWUG contains 8-channel of tmrb. each channel functions independently and the channels oper ate in the same way except for the differences in their specification as shown in table 9-1. table 9-1 differences in the specifications of tmrb modules specification external pins interrupt internal connection channel external clock / capture trigger input pins timer flip-flop output pin capture interrupt tmrb interrupt adc conversion start timer flip-flop output tbxout from sio/uart (txtrg: transfer clock) signal name signal name tmrb0 tb0in tb0out intcap00 intcap01 inttb00 inttb01 tmrb1 tb1in tb1out intcap10 intcap11 inttb10 inttb11 tmrb2 tb2in tb2out intcap20 intcap21 inttb20 inttb21 tmrb3 tb3in tb3out intcap30 intcap31 inttb30 inttb31 tmrb4 tb4in tb4out intcap40 intcap41 inttb40 inttb41 sio0,sio1 tmrb5 - - intcap50 - inttb50 inttb51 inttb51 tmrb6 tb6in tb6out intcap60 intcap61 inttb60 inttb61 tmrb7 tb7in tb7out intcap70 intcap71 inttb70 inttb71 sio2,sio3
page 9-3 TMPM372FWUG 2013/4/15 9.3 configuration each channel consists of a 16-bit up-counter, two 16-bit timer registers (double-buffe red), two 16-bit capture reg- isters, two comparators, a capt ure input control, a timer flip-flop and its associated control circuit. timer operation modes and the timer flip-flop ar e controlled by a register. figure 9-1 tmrbx blo ck diagram (x= 0 to 7) 2 4 8 16 32 t1 t4 t16 t1 t4 t16 tmrbx interrupt inttbx1 inttbx0 tbxin internal data bus run/ clear tbxmod tbxcr tbxmod tbxmod tbxmod prescaler clock: t0 timer flip-flop timer flip-flop output tbxout register buffer0 internal data bus count clock tbxff0 m+ capture control register buffer1 match detect timer flip-flop control capture interrupt intcapx1 tbxcr interrupt mask register tbxim capture interrupt intcapx0 comparator (cp0) comparator (cp1) 16-bit up-counter (uc) capture register1 tbxcp1 capture register0 tbxcp0 up-counter capture register tbxuc prescaler / up-counter control tbxrun tbxcr run/clear status register tbxst timer register0 tbxrg0 timer register1 tbxrg1 register 1 interrupt output register 0 interrupt output overflow interrupt output register 1 interrupt mask register 0 interrupt mask overflow interrupt mask
page 9-4 9. 16-bit timer / event counters (tmrb) 9.4 registers TMPM372FWUG 2013/4/15 9.4 registers 9.4.1 register list according to channel the following table shows the register names and addresses of each channel. channel x base address channel0 0x4001_0000 channel1 0x4001_0040 channel2 0x4001_0080 channel3 0x4001_00c0 channel4 0x4001_0100 channel5 0x4001_0140 channel6 0x4001_0180 channel7 0x4001_01c0 register name (x=0 to 7) address (base+) enable register tbxen 0x0000 run register tbxrun 0x0004 control register tbxcr 0x0008 mode register tbxmod 0x000c flip-flop control register tbxffcr 0x0010 status register tbxst 0x0014 interrupt mask register tbxim 0x0018 up counter capture register tbxuc 0x001c timer register 0 tbxrg0 0x0020 timer register 1 tbxrg1 0x0024 capture register 0 tbxcp0 0x0028 capture register 1 tbxcp1 0x002c
page 9-5 TMPM372FWUG 2013/4/15 9.4.2 tbxen(enable register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symboltbentbhalt------ after reset00000000 bit bit symbol type function 31-8 ? r read as "0". 7 tben r/w tmrbx operation 0: disable 1: enable specifies the tmrb operation. when the operation is disabled, no clock is supplied to the other registers in the tmrb module. this can reduce power c onsumption. (this disables reading from and writing to the other reg- isters except tbxen register.) to use the tmrb, enable the tmrb operation (set to "1") before programming each register in the tmrb mod- ule. if the tmrb operation is executed and then disabled, the settings will be maintained in each register. 6 tbhalt r/w clock operation during debug halt. 0: run 1: stop 5-0 ? r read as "0".
page 9-6 9. 16-bit timer / event counters (tmrb) 9.4 registers TMPM372FWUG 2013/4/15 9.4.3 tbxrun(run register) note 1: when the external trigger start is used (=1), select and before the setting of ==1. note 2: when the counter is stopped (="0") and tbxu c is read, the value which was cap- tured when the counter was operated is read. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-----tbprun-tbrun after reset00000000 bit bit symbol type function 31-3 ? r read as "0". 2 tbprun r/w prescaler operation 0: stop & clear 1: count 1 ? r read as "0". 0 tbrun r/w count operation 0: stop & clear 1: count
page 9-7 TMPM372FWUG 2013/4/15 9.4.4 tbxcr(control register) note 1: do not modify tbxcr during operating tmrb. note 2: when the external trigger start is used (< cssel>=1), select and before the setting of ==1. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol tbwbf - - - i2tb - trgsel cssel after reset00000000 bit bit symbol type function 31-8 ? r read as "0". 7 tbwbf r/w double buffer 0: disable 1: enable 6-5 ? r/w write as "0". 4 ? r read as "0". 3 i2tb r/w operation at idle mode 0: stop 1: operation 2 ? r read as "0". 1 trgsel r/w external trigger select 0: rising edge 1: falling edge 0 cssel r/w counter start select 0: software start 1: external trigger
page 9-8 9. 16-bit timer / event counters (tmrb) 9.4 registers TMPM372FWUG 2013/4/15 9.4.5 tbxmod(mode register) note:do not change tbxmod register while the timer is operating. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - tbrswr tbcp tbcpm tbcle tbclk after reset00100000 bit bit symbol type function 31-7 ? r read as "0". 6 tbrswr r/w writes to timer registers 0 and 1 (when double buffering is enabled) 0: the data transfer to the timer register 0 and 1 is done by corresponding to the up-counter (uc) regardless of the rewriting of the buffer register 0 and 1. 1: to transfer the buffer registers data to the timer registers, the writing of the timer register 0 and 1 together are needed. 5tbcp w capture control by software 0: capture by software 1: don?t care when "0" is written, the capture register 0 (tbxcp0) takes count value. read as "1". 4-3 tbcpm[1:0] r/w capture timing 00: disable capture timing 01: tbxin takes count values into capture register 0 (tbxcp0) upon rising of tbxin pin input. 10: tbxin tbxin takes count values into capture register 0 (tbxcp0) upon rising of tbxin pin input. takes count values into capture register 1 (tbxcp1) upon falling of tbxin pin input. 11: disable capture timing 2 tbcle r/w up-counter control 0: disables clearing of the up-counter 1: enables clearing of the up-counter. clears and controls the up-counter. when "0" is written, it disables clearing of the up-counter. when "1" is written, it clears up counter when there is a match with timer regsiter1 (tbxrg1). 1-0 tbclk[1:0] r/w selects the tmrbx source clock. 00: tbxin pin input 01: t1 10: t4 11: t16
page 9-9 TMPM372FWUG 2013/4/15 9.4.6 tbxffcr(flip-fl op control register) note:do not change tbxffcr register while the timer is operating. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - tbc1t1 tbc0t1 tbe1t1 tbe0t1 tbff0c after reset11000011 bit bit symbol type function 31-8 ? r read as "0". 7-6 ? r read as "1". 5 tbc1t1 r/w tbxff0 reverse trigger when the up-counter value is taken into the tbxcp1. 0: disable trigger 1: enable trigger by setting "1", the timer-flip-flop reverses when the up-counter value is taken into the capture register 1 (tbxcp1). 4 tbc0t1 r/w tbxff0 reverse trigger when the up-counter value is taken into the tbxcp0. 0: disable trigger 1: enable trigger by setting "1", the timer-flip-flop reverses when the up-counter value is taken into the capture register 0 (tbxcp0). 3 tbe1t1 r/w tbxff0 reverse trigger when the up-counter value is matched with tbxrg1. 0: disable trigger 1: enable trigger by setting "1", the timer-flip-flop reverses when the up-counter value is matched with the timer register 1 (tbxrg1). 2 tbe0t1 r/w tbxff0 reverse trigger when t he up-counter value is matched with tbxrg0. 0: disable trigger 1: enable trigger by setting "1", the timer-flip-flop reverses when an up-counter value is matched with the timer register 0 (tbxrg0). 1-0 tbff0c[1:0] r/w tbxff0 control 00: invert reverses the value of tbxff0 (reverse by using software). 01: set sets tbxff0 to "1". 10: clear clears tbxff0 to "0". 11: don't care * this is always read as "11".
page 9-10 9. 16-bit timer / event counters (tmrb) 9.4 registers TMPM372FWUG 2013/4/15 9.4.7 tbxst(status register) note 1: the factors only which is not masked by tbxim out put interrupt request to the cpu.even if the mask setting is done, the flag is set. note 2: the flag is cleared by reading the tbxst register.to clear the flag, tbxst register should be read. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-----inttbofinttb1inttb0 after reset00000000 bit bit symbol type function 31-3 ? r read as "0". 2 inttbof r overflow flag 0: no overflow occurs 1: overflow occurs when an up-counter is overflow, "1" is set. 1 inttb1 r match flag (tbxrg1) 0: no match is detected 1: detects a match with tbxrg1 when a match with the timer register 1 (tbxrg1) is detected,"1" is set. 0 inttb0 r match flag (tbxrg0) 0: no match is detected 1: detects a match with tbxrg0 when a match with the timer register 0 (tbxrg0) is detected, "1" is set.
page 9-11 TMPM372FWUG 2013/4/15 9.4.8 tbxim(interr upt mask register) note:even if mask configuration by tbxim register is valid, the status is set to tbxst register. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-----tbimoftbim1tbim0 after reset00000000 bit bit symbol type function 31-3 ? r read as "0". 2 tbimof r/w overflow interrupt mask 0: disable 1: enable sets the up-counter overflow interrupt to disable or enable. 1 tbim1 r/w match interrupt mask (tbxrg1) 0: disable 1: enable sets the match interrupt mask with the timer register 1 (tbxrg1) to enable or disable. 0 tbim0 r/w match interrupt mask (tbxrg0) 0: disable 1: enable sets the match interrupt mask with the timer register 0 (tbxrg0) to enable or disable.
page 9-12 9. 16-bit timer / event counters (tmrb) 9.4 registers TMPM372FWUG 2013/4/15 9.4.9 tbxuc(up counter capture register) note:when the counter is operated and tbxuc is read, the value of the up counter is captured and read. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol tbuc after reset00000000 7 6 5 4 3 2 1 0 bit symbol tbuc after reset00000000 bit bit symbol type function 31-16 ? r read as "0". 15-0 tbuc[15:0] r captures a value by reading up-counter out. if tbxuc is read, current up-counter value can be captured.
page 9-13 TMPM372FWUG 2013/4/15 9.4.10 tbxrg0(timer register 0) 9.4.11 tbxrg1(timer register 1) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol tbrg0 after reset00000000 7 6 5 4 3 2 1 0 bit symbol tbrg0 after reset00000000 bit bit symbol type function 31-16 ? r read as "0". 15-0 tbrg0[15:0] r/w sets a value comparing to the up-counter. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol tbrg1 after reset00000000 7 6 5 4 3 2 1 0 bit symbol tbrg1 after reset00000000 bit bit symbol type function 31-16 ? r read as "0". 15-0 tbrg1[15:0] r/w sets a value comparing to the up-counter.
page 9-14 9. 16-bit timer / event counters (tmrb) 9.4 registers TMPM372FWUG 2013/4/15 9.4.12 tbxcp0(capture register 0) 9.4.13 tbxcp1(capture register 1) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol tbcp0 after reset00000000 7 6 5 4 3 2 1 0 bit symbol tbcp0 after reset00000000 bit bit symbol type function 31-16 ? r read as "0". 15-0 tbcp0[15:0] r a value captured from the up-counter is read. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol tbcp1 after reset00000000 7 6 5 4 3 2 1 0 bit symbol tbcp1 after reset00000000 bit bit symbol type function 31-16 ? r read as "0". 15-0 tbcp1[15:0] r a value captured from the up-counter is read.
page 9-15 TMPM372FWUG 2013/4/15 9.5 description of operations for each circuit the channels operate in the same way, except for the di fferences in their specificati ons as shown in table 9-1. 9.5.1 prescaler there is a 4-bit prescaler to generate the source clock for up-counter uc. the prescaler input clock t0 is fperiph/1, fperiph/2, fperiph/4, fp eriph/8, fperiph/16 or fperiph/32 selected by cgsyscr in the cg. the peripheral cloc k, fperiph, is either fgear, a clock selected by cgsyscr in the cg, or fc, which is a clock before it is divided by the clock gear. the operation or the stoppage of a prescaler is set with tbxrun where writing "1" starts count- ing and writing "0" clears and stops counting. tabl e 9-2 show prescaler output clock resolutions.
page 9-16 9. 16-bit timer / event counters (tmrb) 9.5 description of operations for each circuit TMPM372FWUG 2013/4/15 table 9-2 prescaler output clock resolutions (fc = 80mhz) select peripheral clock cgsyscr clock gear value cgsyscr select prescaler clock cgsyscr prescaler output clock function t1 t4 t16 0 (fgear) 000 (fc) 000 (fperiph/1) fc/2 1 (0.025 s) fc/2 3 (0.1 s) fc/2 5 (0.4 s) 001 (fperiph/2) fc/2 2 (0.05 s) fc/2 4 (0.2 s) fc/2 6 (0.8 s) 010 (fperiph/4) fc/2 3 (0.1 s) fc/2 5 (0.4 s) fc/2 7 (1.6 s) 011 (fperiph/8) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) 100 (fperiph/16) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 101 (fperiph/32) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 100 (fc/2) 000 (fperiph/1) fc/2 2 (0.05 s) fc/2 4 (0.2 s) fc/2 6 (0.8 s) 001 (fperiph/2) fc/2 3 (0.1 s) fc/2 5 (0.4 s) fc/2 7 (1.6 s) 010 (fperiph/4) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) 011 (fperiph/8) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 100 (fperiph/16) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 101 (fperiph/32) fc/2 7 (1.6 s) fc/2 9 (6.4 s) fc/2 11 (25.6 s) 101 (fc/4) 000 (fperiph/1) fc/2 3 (0.1 s) fc/2 5 (0.4 s) fc/2 7 (1.6 s) 001 (fperiph/2) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) 010 (fperiph/4) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 011 (fperiph/8) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 100 (fperiph/16) fc/2 7 (1.6 s) fc/2 9 (6.4 s) fc/2 11 (25.6 s) 101 (fperiph/32) fc/2 8 (3.2 s) fc/2 10 (12.8 s) fc/2 12 (51.2 s) 110 (fc/8) 000 (fperiph/1) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) 001 (fperiph/2) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 010 (fperiph/4) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 011 (fperiph/8) fc/2 7 (1.6 s) fc/2 9 (6.4 s) fc/2 11 (25.6 s) 100 (fperiph/16) fc/2 8 (3.2 s) fc/2 10 (12.8 s) fc/2 12 (51.2 s) 101 (fperiph/32) fc/2 9 (6.4 s) fc/2 11 (25.6 s) fc/2 13 (102.4 s) 111 (fc/16) 000 (fperiph/1) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 001 (fperiph/2) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 010 (fperiph/4) fc/2 7 (1.6 s) fc/2 9 (6.4 s) fc/2 11 (25.6 s) 011 (fperiph/8) fc/2 8 (3.2 s) fc/2 10 (12.8 s) fc/2 12 (51.2 s) 100 (fperiph/16) fc/2 9 (6.4 s) fc/2 11 (25.6 s) fc/2 13 (102.4 s) 101 (fperiph/32) fc/2 10 (12.8 s) fc/2 12 (51.2 s) fc/2 14 (204.8 s)
page 9-17 TMPM372FWUG 2013/4/15 note 1: the prescaler output clock tn must be selected so that tn < fsys is satisfied (so that tn is slower than fsys). note 2: do not change the clock gear while the timer is operating. note 3: " ? " denotes a setting prohibited. 1 (fc) 000 (fc) 000 (fperiph/1) fc/2 1 (0.025 s) fc/2 3 (0.1 s) fc/2 5 (0.4 s) 001 (fperiph/2) fc/2 2 (0.05 s) fc/2 4 (0.2 s) fc/2 6 (0.8 s) 010 (fperiph/4) fc/2 3 (0.1 s) fc/2 5 (0.4 s) fc/2 7 (1.6 s) 011 (fperiph/8) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) 100 (fperiph/16) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 101 (fperiph/32) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 100 (fc/2) 000 (fperiph/1) ? fc/2 3 (0.1 s) fc/2 5 (0.4 s) 001 (fperiph/2) fc/2 2 (0.05 s) fc/2 4 (0.2 s) fc/2 6 (0.8 s) 010 (fperiph/4) fc/2 3 (0.1 s) fc/2 5 (0.4 s) fc/2 7 (1.6 s) 011 (fperiph/8) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) 100 (fperiph/16) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 101 (fperiph/32) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 101 (fc/4) 000 (fperiph/1) ? fc/2 3 (0.1 s) fc/2 5 (0.4 s) 001 (fperiph/2) ? fc/2 4 (0.2 s) fc/2 6 (0.8 s) 010 (fperiph/4) fc/2 3 (0.1 s) fc/2 5 (0.4 s) fc/2 7 (1.6 s) 011 (fperiph/8) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) 100 (fperiph/16) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 101 (fperiph/32) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 110 (fc/8) 000 (fperiph/1) ? ? fc/2 5 (0.4 s) 001 (fperiph/2) ? fc/2 4 (0.2 s) fc/2 6 (0.8 s) 010 (fperiph/4) ? fc/2 5 (0.4 s) fc/2 7 (1.6 s) 011 (fperiph/8) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) 100 (fperiph/16) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 101 (fperiph/32) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 111 (fc/16) 000 (fperiph/1) ? ? fc/2 5 (0.4 s) 001 (fperiph/2) ? ? fc/2 6 (0.8 s) 010 (fperiph/4) ? fc/2 5 (0.4 s) fc/2 7 (1.6 s) 011 (fperiph/8) ? fc/2 6 (0.8 s) fc/2 8 (3.2 s) 100 (fperiph/16) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 101 (fperiph/32) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) table 9-2 prescaler output clock resolutions (fc = 80mhz) select peripheral clock cgsyscr clock gear value cgsyscr select prescaler clock cgsyscr prescaler output clock function t1 t4 t16
page 9-18 9. 16-bit timer / event counters (tmrb) 9.5 description of operations for each circuit TMPM372FWUG 2013/4/15 9.5.2 up-counter (uc) uc is a 16-bit binary counter. ? source clock uc source clock, specified by tbxmod, can be selected fr om either three types t1, t4, t16 of prescaler output clock or th e external clock of the tbxin pin. ? count start / stop counter operation is specified by tbxrun< tbrun>. uc starts counting if = "1", and stops counting and clears counter value if = "0". ? timing to clear uc 1. when a match is detected by setting tbxmod = "1", uc is cleared if when the comparator detects a match between counter value and the value set in tbxr g1. uc operates as a free-running counter if tbxmod = "0". 2. when uc stops uc stops counting and clears counter value if tbxrun = "0". ? uc overflow if uc overflow occurs, the inttbx0 overflow interrupt is generated. 9.5.3 timer register s (tbxrg0, tbxrg1) tbxrg0 and tbxrg1 are registers for setting values to compare with up-counter values and two registers are built into each channel. if the comp arator detects a match between a value set in this timer register and that in a uc up-counter, it outputs the match detection signal. tbxrg0 and tbxrg1 are consisted of the double-buffe red configuration which are paired with register buffers. the double buffering is disabled in the initial state. controlling double buffering disable or enable is specified by tbxcr bit. if = "0", the double buffering becomes disable. if = "1", it becomes enable. when the double buffering is enabled, a data transfer from the regi ster buffer to the timer register (tbxrg0/1) is done in the case that uc is matched with tbxrg1. when the counter is stopped even if double buffering is enabled, the double buffering operates as a single buffer, and an immediate da ta can be written to the tbxrg0 and tbxrg1. 9.5.4 capture this is a circuit that controls the timing of latching values from the uc up-counter into the tbxcp0 and tbxcp1 capture registers. the timing with which to latch data is specified by tbxmod. software can also be used to import values from th e uc up-counter into the captu re register; specifically, uc values are taken into the tbxcp0 capture regi ster each time "0" is written to tbxmod.
page 9-19 TMPM372FWUG 2013/4/15 9.5.5 capture register (tbxcp0, tbxcp1) this register captures an up-counter (uc) value. 9.5.6 up counter capture register (tbxuc) other than the capturing functions shown above, the current count value of the uc can be captured by read- ing the tbxuc registers. 9.5.7 comparators (cp0, cp1) this register compares with the up-counter (uc) and the value setting of the timer register (tbxrg0 and tbxrg1) to detect whether there is a match or not. if a match is detected, inttbx0 and inttbx1 are gener- ated. 9.5.8 timer flip-flop (tbxff0) the timer flip-flop (tbxff0) is reversed by a match sign al from the comparator and a latch signal to the cap- ture registers. it can be enabled or disabled to reverse by setting the tbxffcr. the value of tbxff0 becomes undefi ned after a reset. the flip-flop can be reversed by writing "00" to tbxffcr. it can be set to "1" by writing "01," and can be cleared to "0" by writing "10." the value of tbxff0 can be output to the timer output pin (tbxout). if the timer output is performed, the corresponding port settings must be programmed beforehand. 9.5.9 capture interrupt (intcapx0, intcapx1) interrupts intcapx0 and intcapx1 can be generated at the timing of latching values from the uc up- counter into the tbxcp0 and tbxcp1 capture registers. the interrupt timing is specified by the cpu.
page 9-20 9. 16-bit timer / event counters (tmrb) 9.6 description of operations for each mode TMPM372FWUG 2013/4/15 9.6 description of operations for each mode 9.6.1 16-bit interval timer mode in the case of generating constant period interrupt, se t the interval time to the timer register (tbxrg0) to generate the inttbx0 interrupt. same as tbxrg0, inttbx 1 interrupt is generated by setting different inter- val time value to tbxrg1 timer resister. note:x; don?t care ? ; no change 9.6.2 16-bit ev ent counter mode it is possible to make it the event counter by using an input clock as an extern al clock (tbxin pin input). the up-counter counts up on the rising edge of tbxin pin input. it is possible to read the count value by cap- turing value using software and reading the captured value. note:x; don?t care ? ; no change 76543210 tbxen 1 x x x x x x x enables tmrbx operation. tbxrun x x x x x 0 x 0 stops count operation. interrupt set-enable register * * * * * * * * permits inttbx1 interrupt by setting corresponding bit to "1". tbxffcr xx000011 disable to tbxff0 reverse trigger. tbxmod x 0 1 0 0 1 * * changes to prescaler output clock as input clock. specifies capture function to disable. (** = 01, 10, 11) tbxrg1 * * * * * * * * specifies a time interval. (16 bits) ******** tbxrun *****1x1 starts tmrbx. 76543210 tbxen 1 x x x x x x x enables tmrbx operation. tbxrun x x x x x 0 x 0 stops count operation. set port registers. allocates corresponding port to tbxin. tbxffcr xx000011 disable to tbxff0 reverse trigger. tbxmod x 0 1 0 0 0 0 0 changes to tbxin as an input clock. tbxrun *****1x1 starts tmrbx. tbxmod x 0 0 0 0 0 0 0 software capture is done.
page 9-21 TMPM372FWUG 2013/4/15 9.6.3 16-bit ppg (programmable pulse generation) output mode square waves with any frequency and any duty (pro grammable square waves) can be output. the output pulse can be either lo w-active or high-active. programmable square waves can be output from the tbxout pin by triggering the timer flip-flop (tbxff) to reverse when the set value of the up-counter (uc) matches the set values of the timer registers (tbxrg0 and tbxrg1). note that the set values of tbxrg0 and tbxrg1 must satisfy the following requirement: set value of tbxrg0 < set value of tbxrg1 figure 9-2 example of output of programmable pulse generation (ppg) in this mode, by enabling the double buffering of tbxrg0, the value of register buffer 0 is shifted into tbxrg0 when the set value of the up-counter matches the set value of tbxrg1. this facilitates handling of small duties. figure 9-3 register buffer operation tbxout pin match with tbxrg0 (inttbx0 interrupt) match with tbxrg1 (inttbx1 interrupt) q 2 q 1 match with tbxrg1 tbxrg0 (compare value) q 3 q 2 register buffer trigger to shift to tbxrg1 write tbxrg0 up-counter= q1 up-counter= q2 match with tbxrg0 q 5 q 4 tbxrg1 (compare value) q 6 q 5 register buffer write tbxrg1
page 9-22 9. 16-bit timer / event counters (tmrb) 9.6 description of operations for each mode TMPM372FWUG 2013/4/15 the block diagram of this mode is shown below. figure 9-4 block diagram of 16-bit ppg mode each register in the 16-bit ppg output mo de must be programmed as listed below. note:x; don?t care ? ; no change 76543210 tbxen 1 x x x x x x x enables tmrbx operation. tbxrun x x x x x 0 x 0 stops count operation. tbxcr 00 ? x ? x 0 0 disables double buffering. tbxrg0 ******** specifies a duty. (16 bits) ******** tbxrg1 ******** specifies a cycle. (16 bits) ******** tbxcr 100x ? x 0 0 enables the tbxrg0 double buffering. (changes the duty/cycle when the inttbx0 interrupt is gener- ated) tbxffcr x x 0 0 1 1 1 0 specifies to trigger tbxff0 to reverse when a match with tbxrg0 or tbxrg1 is detected, and sets the initial value of tbxff0 to "0". tbxmod x 0 1 0 0 1 * * designates the prescaler output clock as the input clock, and disables the capture function. uc is cleared to match tbxrg1. (** = 01, 10, 11) set port registers. allocates co rresponding port to tbxout. tbxrun *****1x1 starts tmrbx. selector selector internal data bus tbxcr write tbxrg0 tbxout (ppg output) tbxrun match tbxin -t1 -t4 -t16 tbxrg0 clear 16-bit up-counter uc tbxrg1 f/f (tbxff0) selector write tbxrg1 tbxcr 16-bit comparator 16-bit comparator register buffer 0 register buffer 1
page 9-23 TMPM372FWUG 2013/4/15 9.6.4 external trigger programmable pulse genera tion output mode (ppg) using an external count start trigger enables one-shot pulse generation with a short delay. the 16-bit up-counter (uc) is programmed to count up on the rising edge of the tbxin pin (tbxcr[1:0] = "01"). the tbxrg0 is loaded with the pulse delay (d), and the tbxrg1 is loaded with the sum of the tbxrg0 value (d) and the pulse width (p). the above settings must be done while the 16-bit up-counter is stopped (tbxrun = 0). to enable the trigger for timer flip-flop, sets tbx ffcr to "11". with this setting, the timer flip-flop reverses when 16-bit up-count er (uc) corresponds to tbxrg0 or tbxrg1. sets tbxrun to "1" to enable the count-up by an external trigger. after the generation of one-shot pulse by the external tr igger, to disable reverse of the timer flip-flop or to stop 16bit counter by tbxrun setting. symbols (d) and (p) used in the text correspond to symbols d and p in figure 9-5. figure 9-5 one-shot pulse gener ation using an exte rnal count start tr igger (with a delay) counter clock (internal clock) timer output tbxout pin tbxin input pin (external trigger pulse) match with tbxrg0 match with tbxrg1 0 (p) d d + p reverse the counter starts at the rising edge of external trigger. inttbx1 generation pulse width (d) delay time inttbx0 generation reverse
page 9-24 9. 16-bit timer / event counters (tmrb) 9.7 applications using the capture function TMPM372FWUG 2013/4/15 9.7 applications usin g the capture function the capture function can be used to develop many applications, including those described below: 1. one-shot pulse output triggered by an external pulse 2. pulse width measurement 9.7.1 one-shot pulse output triggered by an external pulse one-shot pulse output triggered by an external pulse is carried out as follows: the 16-bit up-counter is made to count up by putting it in a free-running state using the prescaler output clock. an external pulse is input through the tbxin pi n. a trigger is generated at the rising of the external pulse by using the capture function and the value of the up-counter is taken into the capture registers (tbxcp0). the cpu must be programmed so that an interrupt intcap x0 is generated at the risi ng of an external trigger pulse. this interrupt is used to set the timer register s (tbxrg0) to the sum of the tbxcp0 value (c) and the delay time (d), (c + d), and set the timer registers (tbxrg1) to the sum of the tbxrg0 values and the pulse width (p) of one-shot pulse, (c + d + p).[tbxrg1 change must be completed before the next match.] in addition, the timer flip-flop control registers(tbxffcr) must be set to "11". this enables triggering the timer flip-flop (tbxff0) to reverse when tbxuc matches tbxrg0 and tbxrg1. this trigger is disabled by the inttbx0 / inttbx1 interrupt after a one-shot pulse is output. symbols (c), (d) and (p) used in the text correspond to symbols c, d and p in figure 9-6. figure 9-6 one-shot pu lse output (with delay) count clock (internal clock) timer output tbxout pin tbxin pin input (external trigger pulse) match with tbxrg0 match with tbxrg1 c (p) c + d c + d + p enable reverse enable reverse put the counter in a free-running state. taking data into the capture register (tbxcp0). inttbx1 generation disable reverse when data is taken into tbxcp0. pulse width (d) delay time inttbx0 generation intcapx0 generation
page 9-25 TMPM372FWUG 2013/4/15 the followings show the settings in the case that 2 ms width one-shot pulse is output after 3ms by triggering tbxin input at the rising edge. ( t1 is selected for counting.) note:x; don?t care ? ; no change if a delay is not required, tbxff0 is reversed when data is taken into tbxcp0, and tbxrg1 is set to the sum of the tbxcp0 value (c) and the one-shot pulse width (p), (c + p), by generating the intcapx0 interrupt. tbxrg1 change must be completed before the next match. tbxff0 is enabled to reverse when uc matches with tbxrg1, and is disabled by generating the inttbx1 interrupt. figure 9-7 one-shot pulse output triggered by an external pulse (without delay) 76543210 [[main processing] capture setting by tbxin set port registers. allocates corresponding port to tbxin. tbxen 1 x x x x x x x enables tmrbx operation. tbxrun x x x x x 0 x 0 stops count operation. tbxmod x0101001 changes source clock to t1. fetches a count value into the tbxcp0 at the rising edge of tbxin. tbxffcr x x 0 0 0 0 1 0 clears tbxff0 reverse trigger and disables. set port registers. allocates corresponding port to tbxout. interrupt set-enable register ******** permits to generate interrupts specified by intcapx0 inter- rupt corresponding bit by setting to "1". tbxrun *****1x1 starts the tmrbx module. [processing of intcapx0 interrupt service routine] pulse output setting tbxrg0 ******** sets count value.(tbxcap0 + 3ms/ t1) ******** tbxrg1 ******** sets count value.(tbxcap0 + (3+2)ms/ t1) ******** tbxffcr xx ?? 11 ?? reverses tbxff0 if uc consistent with tbxrg0 and tbxrg1. tbxim xxxxx1 01 masks except tbxrg1 correspondence interrupt. interrupt set-enable register ******** permits to generate interrupt specified by inttbx interrupt corresponding bit setting to "1". [processing of inttbx interrupt service routine] output disable tbxffcr xx ?? 00 ?? clears tbxff0 reverse trigger setting. ******** prohibits interrupts specified by inttbx interrupt correspond- ing bit by setting to "1". count clock (prescaler output clock) timer output tbxout pin tbxin input (external trigger pulse) match with tbxrg1 c (p) c + p enable reverse inttbx1 generation enable reverse when data is taken into tbxcp0. taking data into the capture register tbxcp0. taking data into the capture register tbxcp1. disable reverse when data is taken into tbxcp1. pulse width intcapx0 generation
page 9-26 9. 16-bit timer / event counters (tmrb) 9.7 applications using the capture function TMPM372FWUG 2013/4/15 9.7.2 pulse width measurement by using the capture function, the "high" level width of an external pulse can be measured. specifically, by putting it in a free-running state using the prescaler outp ut clock, an external pulse is input through the tbxin pin and the up-counter (uc) is made to count up. a trigger is generated at each rising and falling edge of the external pulse by using the capture function and the valu e of the up-counter is taken into the capture registers (tbxcp0, tbxcp1). the cpu must be programmed so that intcapx1 is generated at the falling edge of an external pulse input through the tbxin pin. the "high" level pulse width can be calculated by multiplying the difference between tbxcp0 and tbxcp1 by the clock cycle of an internal clock. for example, if the difference betw een tbxcp0 and tbxcp1 is 100 and the cycle of the prescaler output clock is 0.5 s, the pulse width is 100 0.5 s = 50 s. caution must be exercised when measuring pulse wi dths exceeding the uc maximum count time which is dependant upon the source clock used. the measurement of such pulse widths must be made using software. the "low" level width of an external pulse can also be measured. in such cases, the difference between c2 generated the first time and c1 generated the second ti me is initially obtained by performing the second stage of intcapx0 interrupt processing as shown in figure 9-8 and this difference is multiplied by the cycle of the prescaler output clock to obtain the "low" level width. figure 9-8 pulse width measurement prescaler output clock taking data into tbxcp1 tbxin pin input (external pulse) taking data into tbxcp0 c1 c1 c1 c2 c2 c2 intcapx1 intcapx0
page 10-1 TMPM372FWUG 2013/4/15 10. serial channel (sio/uart) 10.1 overview this device has two mode for the serial channel, one is the synchronous communication mode (i/o interface mode), and the other is the asynchron ous communication mode (uart mode). their features are given in the following. ? transfer clock - dividing by the prescaler, from the peripheral clock ( t0) frequency into 1/2, 1/8, 1/32, 1/128. - make it possible to divide from the prescaler output clock frequency into 1-16. - make it possible to divide from the prescaler out put clock frequency into 1, n+m/16 (n=2-15, m=1- 15). (only uart mode) - the usable system clock (only uart mode). ? double buffer /fifo the usable double buffer function, and the usable fifo buffers of transmit and receive in all for maxi- mum 4-byte. ? i/o interface mode - transfer mode: the half duplex (transmit/receive), the full duplex - clock: output (fixed rising edge) /i nput (selectable rising/falling edge) - make it possible to specify the interval time of continuous transmission. ? uart mode - data length: 7 bits, 8bits, 9bits - add parity bit (to be against 9bits data length) - serial links to use wake-up function - handshaking function with cts pin in the following explanation, "x" represents channel number. 10.2 difference in the spec ifications of sio modules TMPM372FWUG has four sio channels. each channel functions independently. the used pins , interrupt, dma request and uart source clock in each channel are collected in the following. table 10-1 difference in the specifications of sio modules pin name interrupt uart source clock txd rxd ctsx / sclkx receive interrupt transmit interrupt channel 0 pe0 pe1 pe2 intrx0 inttx0 tb4out channel 1 pa5 pa6 pa4 intrx1 inttx1 tb4out channel 2 pd5 pd6 pd4 intrx2 inttx2 tb7out channel 3 pf3 pf4 pf2 intrx3 inttx3 tb7out
page 10-2 10. serial channel (sio/uart) 10.3 configuration TMPM372FWUG 2013/4/15 10.3 configuration figure 10-1 shows sio block diagram. figure 10-1 sio block diagram t0 f sys - t1 - t4 - t16 - t64 - t1 scxbrcr tbxout (from tmrbx) scxbrcr scxcr sioclk scxmod0 scxmod0 txdclk scxcr scxmod0 scxmod0 scxmod0 scxbrcr scxbradd prescaler uart mode sclkx input sclkx output rxdx txdx interrupt request intrxx interrupt request inttxx 1 2 scxcr i/o interface mode ctsx rxdclk 2 4 8 16 32 64 128 - t4 - t16 - t64 baud rate generator i/o interface mode transmission counter (only at uart : 16) serial channel interrupt control transmission control recive control recive shift register tb8 transmission buffer (scxbuf) rb8 recive buffer (scxbuf) parity control fifo control error flag fifo control int e rn a l da t a bus int e rn a l da t a bus internal data bus selector selector selector selector transmission shift register divider serial clock generation circuit recive counter (only at uart : 16)
page 10-3 TMPM372FWUG 2013/4/15 10.4 registers description 10.4.1 registers list in each channel the each channel registers and addresses are shown below. note: do not modify any control register when data is being transmitted or received. channel x base address channel0 0x4002_0080 channel1 0x4002_00c0 channel2 0x4002_0100 channel3 0x4002_0140 register name (x=0,1,2,3) address (base+) enable register scxen 0x0000 buffer register scxbuf 0x0004 control register scxcr 0x0008 mode control register 0 scxmod0 0x000c baud rate generator control register scxbrcr 0x0010 baud rate generator control register 2 scxbradd 0x0014 mode control register 1 scxmod1 0x0018 mode control register 2 scxmod2 0x001c rx fifo configuration register scxrfc 0x0020 tx fifo configuration register scxtfc 0x0024 rx fifo status register scxrst 0x0028 tx fifo status register scxtst 0x002c fifo configuration register scxfcnf 0x0030
page 10-4 10. serial channel (sio/uart) 10.4 registers description TMPM372FWUG 2013/4/15 10.4.2 scxen (enable register) note:when scxen is cleared to "0" (disable sio oper ation) or the operation mode transits to idle mode by setting scxmod1 to "0", it is necessary to reset scxtfc. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-------sioe after reset00000000 bit bit symbol type function 31-1 ? r read as 0. 0 sioe r/w sio operation 0: disabled 1: enabled specified the sio operation. to use the sio, set = "1". when the operation is disabled, no cl ock is supplied to the other register s in the sio module. this can reduce the power consumption. if the sio operation is executed and then disabled, the se ttings will be maintained in each register except for scxtfc.
page 10-5 TMPM372FWUG 2013/4/15 10.4.3 scxbuf (buffer register) scxbuf works as a transmit buffer or fifo for write operat ion and as a receive bu ffer or fifo for read operation. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol tb / rb after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 tb[7:0] / rb[7:0] r/w [write] tb : transmit buffer / fifo [read] rb : receive buffer / fifo
page 10-6 10. serial channel (sio/uart) 10.4 registers description TMPM372FWUG 2013/4/15 10.4.4 scxcr (control register) note: any error flag (oerr, perr, ferr) is cleared to "0" when read. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol rb8 even pe oerr perr ferr sclks ioc after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7 rb8 r receive data bit 8 (for uart) 9th bit of the received data in the 9 bits uart mode. 6 even r/w parity (for uart) 0: odd 1: even selects even or odd parity. "0" : odd parity, "1" : even parity. the parity bit may be used only in the 7- or 8-bit uart mode. 5 pe r/w add parity (for uart) 0: disabled 1: enabled controls enabling/ disabling parity. the parity bit may be used only in the 7- or 8-bit uart mode. 4 oerr r overrun error flag (note) 0: normal operation 1: error 3 perr r parity / under-run error flag (note) 0: normal operation 1: error 2 ferr r framing error flag (note) 0: normal operation 1: error 1 sclks r/w selects input clock edge for data transmission and reception. (for i/o interface) 0: data in the transmit buffer is sent to txdx pin one bit at a time on the falling edge of sclkx. data from rxdx pin is received in the receiv e buffer one bit at a time on the rising edge of sclkx. in this case, the sclk starts from high level. 1: data in the transmit buffer is sent to txdx pin one bit at a time on the rising edge of sclkx. data from rxdx pin is received in the receiv e buffer one bit at a time on the falling edge of sclkx. in this case, the sclk starts from low level. set to "0" in the clock output mode. 0 ioc r/w selecting clock (for i/o interface) 0: baud rate generator 1: sclk pin input
page 10-7 TMPM372FWUG 2013/4/15 10.4.5 scxmod0 (mode control register 0) note 1: with set to "0", set each mode regist er (scxmod0, scxmod1 and scxmod2). then set to "1". note 2: do not stop the receive operation (by setting scxmod0 = "0") when data is being received. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol tb8 ctse rxe wu sm sc after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7 tb8 r/w transmit data bit 8 (for uart) writes the 9th bit of transmit data in the 9 bits uart mode. 6 ctse r/w handshake function control (for uart) 0: cts disabled 1: cts enabled controls handshake function. setting "1" enables handshake function using cts pin. 5 rxe r/w receive control (note1)(note2) 0: disabled 1: enabled 4 wu r/w wake-up function (for uart) 0: disabled 1: enabled this function is available only at 9-bit uart m ode. in other mode, this function has no meaning. in it is enabled, interrupt only when rb9 = "1" at 9-bit uart mode. 3-2 sm[1:0] r/w specifies transfer mode. 00: i/o interface mode 01: 7-bit length uart mode 10: 8-bit length uart mode 11: 9-bit length uart mode 1-0 sc[1:0] r/w serial transfer clock (for uart) 00: timer tbxout (refer to table 10-1) 01: baud rate generator 10: internal clock fsys 11: external clock (sclk input) (as for the i/o interface mode, the serial transfer clock can be set in the control register (scxcr).
page 10-8 10. serial channel (sio/uart) 10.4 registers description TMPM372FWUG 2013/4/15 10.4.6 scxmod1 (mode control register 1) note 1: specify the all mode first and then enable the bit. note 2: do not stop the transmit operation (by setting = "0") when data is being transmitted. note 3: when scxen is cleared to "0" (disable si o operation) or the operation mode transits to idle mode by setting scxmod1 to "0", it is necessary to reset scxtfc. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol i2s0 fdpx txe sint - after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7 i2s0 r/w idle 0: stop 1: operate specifies the idle mode operation. 6-5 fdpx[1:0] r/w transfer mode setting 00: transfer prohibited 01: half duplex (receive) 10: half duplex (transmit) 11: full duplex configures the transfer mode in the i/o interface m ode. also configures the fifo if it is enabled. in the uart mode, it is used only to specify the fifo configuration. 4 txe r/w transmit control (note1)(note2) 0 :disabled 1: enabled this bit enables transmission and is valid for all the transfer modes. 3-1 sint[2:0] r/w interval time of continuous transmission (for i/o interface) 000: none 001: 1sclk 010: 2sclk 011: 4sclk 100: 8sclk 101: 16sclk 110: 32sclk 111: 64sclk this parameter is valid only for the i/o interface mode when sclk pin output is selected. in other modes, this function has no meaning. specifies the interval time of continuous transmission when double buffering or fifo is enabled in the i/o in- terface mode. 0 ? r/w write a "0".
page 10-9 TMPM372FWUG 2013/4/15 10.4.7 scxmod2 (mode control register 2) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol tbemp rbfll txrun sblen drchg wbuf swrst after reset10000000
page 10-10 10. serial channel (sio/uart) 10.4 registers description TMPM372FWUG 2013/4/15 note 1: while data transmission is in progress, any softwa re reset operation must be executed twice in succession. note 2: a software reset requires 2 clocks-duration at the time between the end of recognition and the start of exe- cution of software reset instruction. bit bit symbol type function 31-8 ? r read as 0. 7 tbemp r transmit buffer empty flag. 0: full 1: empty if double buffering is disabled, this flag is insignificant. this flag shows that the transmit double buffers are em pty. when data in the transmit double buffers is moved to the transmit shift register and the double buffers are empty, this bit is set to "1". writing data again to the double buffers sets this bit to "0". 6 rbfll r receive buffer full flag. 0: empty 1: full if double buffering is disabled, this flag is insignificant. this is a flag to show that t he receive double buffers are full. when a receive operation is completed and received data is moved from the receive shift register to the receive double buffers, this bit changes to "1" wh ile reading this bit changes it to "0". 5 txrun r in transmission flag 0: stop 1: operate this is a status flag to show t hat data transmission is in progress. and bits indicate the following status. status 1 ? transmission in progress 0 1 transmission completed 0 wait state with data in transmit buffer 4 sblen r/w stop bit (for uart) 0 : 1-bit 1 : 2-bit this specifies the length of transmission stop bit in the uart mode. on the receive side, the decision is made using only a single bit regardless of the setting. 3 drchg r/w setting transfer direction 0: lsb first 1: msb first specifies the direction of data transfer in the i/o interface mode. in the uart mode, set this bit to lsb first. 2 wbuf r/w double-buffer 0: disabled 1 : enabled this parameter enables or disables the transmit/receive double buffers to transmit (in both sclk output/input modes) and receive (in sclk output mode) data in the i/o interface mode and to transmit data in the uart mode. when receiving data in the i/o interface mode (sclk input) and uart mode, double buffering is enabled in both cases that 0 or 1 is set to bit. 1-0 swrst[1:0] r/w software reset overwriting "01" in place of "10" generates a software reset. when this software reset is executed, the following bits are initialized : register bit scxmod0 scxmod1 scxmod2 , , scxcr , , the transmit/receive circuit and the fifo become initial state (see note1 and note2).
page 10-11 TMPM372FWUG 2013/4/15 10.4.8 scxbrcr (baud rate generator control register), scxbra dd (baud rate gen- erator control register 2) the division ratio of the baud rate generator can be specified in the registers shown below. scxbrcr 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - bradde br0ck br0s after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7 ? r/w write "0". 6 bradde r/w n + (16 ? k)/16 divider function (for uart) 0: disabled 1: enabled this division function can only be used in the uart mode. 5-4 br0ck[1:0] r/w select input clock to the baud rate generator 00: t1 01: t4 10: t16 11: t64 3-0 br0s[3:0] r/w division ratio "n" 0000: 16 0001: 1 0010: 2 ... 1111: 15
page 10-12 10. serial channel (sio/uart) 10.4 registers description TMPM372FWUG 2013/4/15 table 10-2 lists the settings of baud rate generator division ratio. note 1: to use the "n + (16 - k)/16" division function, be sure to set to "1" after setting the k value to . the "n + (16 - k)/16" division function can only be used in the uart mode. note 2: as a division ratio, 1 ("0001") or 16 ("0000") can not be applied to n when using the "n + (16 - k)/16" division function in the uart mode. note 3: the division ratio "1" of the baud rate generator can be specified only when the double buffering is used in the i/o interface mode. note 4: specifying "k = 0" is prohibited. scxbradd 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol---- br0k after reset00000000 bit bit symbol type function 31-4 ? r read as 0. 3-0 br0k[3:0] r/w specify k for the "n + (16 ? k)/16" division (for uart) 0000: prohibited 0001: k = 1 0010: k = 2 ... 1111: k = 15 table 10-2 setting division ratio = "0" = "1" (note1) (only uart mode) specify "n" (note2) (note3) no setting required specify "k" (note4) division ratio divide by n n + (16 ? k) 16 glylvlrq
page 10-13 TMPM372FWUG 2013/4/15 10.4.9 scxfcnf (fifo c onfiguration register) note 1: regarding tx fifo, the maximum number of byte s being configured is always available. the avail- able number of bytes is the bytes already written to the tx fifo. note 2: the fifo can not use in 9bit uart mode. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - rfst tfie rfie rxtxcnt cnfg after reset00000000 bit bit symbol type function 31-8 - r read as 0 7-5 - r/w be sure to write "000" 4 rfst r/w bytes used in rx fifo 0:maximum 1:same as fill level of rx fifo when rx fifo is enabled, the number of rx fifo bytes to be used is selected (note1) 0: the maximun number of bytes of the fifo configured (see also ). 1: same as the fill level for receive inte rrupt generation specified by scxrfc 3 tfie r/w tx interrupt for tx fifo 0: disabled 1: enabled when tx fifo is enabled, transmit interrupts are enabled or disabled by this parameter. 2 rfie r/w rx interrupt for rx fifo 0: disabled 1: enabled when rx fifo is enabled, receive interrupts are enabled or disabled by this parameter. 1 rxtxcnt r/w automatic disable of / 0: none 1: auto disabled controls automatic disabling of transmission and reception. setting "1" enables to operate as follows half duplex rx when receive shift register, the receive buffer and the rx fifo are filled, scxmod0 is automatically set to "0" to inhibit further reception. half duplex tx when the tx fifo, the transmit buffer and the transmit shift register is empty, scxmod1 is automatically set to "0" to inhibit further transmission. full duplex when either of the above two conditions is satisfied, / are automati- cally set to "0" to inhibit further transmission and reception. 0 cnfg r/w enables fifo (note2) 0: disabled 1: enabled if enabled, the scxmod1 setting aut omatically configures fifo as follows: (the type of tx/rx can be specified in the mode control register 1 scxmod1). half duplex rx rx fifo 4byte half duplex tx tx fifo 4byte full duplex rx fifo 2byte + tx fifo 2byte
page 10-14 10. serial channel (sio/uart) 10.4 registers description TMPM372FWUG 2013/4/15 10.4.10scxrfc (rx fifo configuration register) note:to use tx/rx fifo buffer, tx/rx fifo must be clea red after setting the sio transfer mode (half duplex/full duplex) and enabling fifo (scxfcnf = "1"). 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbolrfcsrfis---- ril after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7 rfcs w rx fifo clear (note) 1: clears rx fifo when scxrfc is set to "1", the receive fifo is cleared and scxrst is "000". and also the read pointer is initialized. 6 rfis r/w select interrupt generation condition 0: an interrupt is generated when the data reaches to the specified fill level. 1: an interrupt is generated when the data reaches to the specified fill level or t he data exceeds the specified fill level at the time data is read. 5-2 ? r read as 0. 1-0 ril[1:0] r/w fifo fill level to generate rx interrupts half duplex full duplex 00 4byte 2byte 01 1byte 1byte 10 2byte 2byte 11 3byte 1byte
page 10-15 TMPM372FWUG 2013/4/15 10.4.11scxtfc (tx fifo configuration register) (note2) note 1: to use tx/rx fifo buffer, tx/rx fifo must be cleared after setting the sio transfer mode (half duplex/full duplex) and enabling fifo (scxfcnf = "1"). note 2: after you perform the following operations, configure the scxtfc register again. scxen = "0" (sio operation stop) conditions are as follows:scxmod1 = "0" (operation is prohibited in idle mode) and releas- ing the low power consumption mode which started by the wfi (wait for interrupt) instruction. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symboltfcstfis---- til after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7 tfcs w tx fifo clear (note 1) 1: clears tx fifo. when scxtst is set to "1", the transmit fifo is cleared and scxrst is "000". and also the write pointer is initialized. 6 tfis r/w selects interrupt generation condition. 0: an interrupt is generated when the data reaches to the specified fill level. 1: an interrupt is generated when the data reaches to the specified fill level or the data can not reach the spec- ified fill level at the time new data is read. 5-2 ? r read as 0. 1-0 til[1:0] r/w fifo fill level to generate tx interrupts. other than full duplex full duplex 00 empty empty 01 1 byte 1 byte 10 2 byte empty 11 3 byte 1 byte
page 10-16 10. serial channel (sio/uart) 10.4 registers description TMPM372FWUG 2013/4/15 10.4.12scxrst (rx fifo status register) note: the bit is cleared to "0" when receive data is read from the scxbuf register. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbolror---- rlvl after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7 ror r rx fifo overrun (note) 0: not generated 1: generated 6-3 ? r read as 0. 2-0 rlvl[2:0] r status of rx fifo fill level. 000: empty 001: 1 byte 010: 2 byte 011: 3 byte 100: 4 byte
page 10-17 TMPM372FWUG 2013/4/15 10.4.13scxtst (tx fifo status register) note: the bit is cleared to "0" when transmit data is written to the scxbuf register. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symboltur---- tlvl after reset10000000 bit bit symbol type function 31-8 ? r read as 0. 7 tur r tx fifo under run (note) 0: not generated 1: generated. 6-3 ? r read as 0. 2-0 tlvl[2:0] r status of tx fifo fill level. 000: empty 001: 1 byte 010: 2 byte 011: 3 byte 100: 4 byte
page 10-18 10. serial channel (sio/uart) 10.5 operation in each mode TMPM372FWUG 2013/4/15 10.5 operation in each mode table 10-3 shows the modes and data formats. mode 0 is a synchronous comm unication and can be used to extend i/o. this mode transmits and receives data in synchronization with sclk. sclk can be used for both input and output. the direction of data transfer can be se lected from lsb first and msb first. th is mode is not allowed either to use parity bits or stop bits. the mode 1, mode 2 and mode 3 are asynchronous modes and the transfer direction is fixed to the lsb first. parity bits can be added in the mode 1 and mode 2. the mode 3 has a wakeup function in which the master control- ler can start up slave controllers via th e serial link (multi-controller system). stop bit in transmission can be select ed from 1 bit and 2 bits. the stop bit length in reception is fixed to a one bit. table 10-3 mode and data format mode mode type data length transfer direction specifies whether to use parity bits. stop bit length (transmit) mode 0 synchronous communication mode (io interface mode) 8 bit lsb first/msb first - - mode 1 asynchronous communica- tion mode (uart mode) 7 bit lsb first 1 bit or 2 bit mode 2 8 bit mode 3 9 bit
page 10-19 TMPM372FWUG 2013/4/15 10.6 data format 10.6.1 data format list figure 10-2 shows data format. figure 10-2 data format mode1 (7bits uart mode) bit 0 1 2 3 4 5 6 stop start without parity bit 0 1 2 3 4 5 6 parity stop start with parity mode2 (8bits uart mode) bit 0 1 2 3 4 5 6 start 7 stop without parity bit 0 1 2 3 4 5 6 7 parity stop start with parity stop bit 0 1 2 3 4 5 6 start 7 8 bit 0 1 2 3 4 5 6 7 bit 8 stop (wake-up) start mode3 (9bits uart mode) bit 8 = 1 represents address. (select code) bit 8 = 0 represents data. 1 bit 0 2 3 4 5 6 mode0 (i/o interface mode) / lsb first transmission direction 7 6 bit 7 5 4 3 2 1 mode0 (i/o interface mode ) / msb first transmission direction 0
page 10-20 10. serial channel (sio/uart) 10.6 data format TMPM372FWUG 2013/4/15 10.6.2 parity control the parity bit can be added only in the 7 or 8-bit uart mode. setting "1" to scxcr enables the parity. the bit of scxcr select s either even or odd parity. 10.6.2.1 transmission upon data transmission, the parity control circuit automatically generates the parity with the data in the transmit buffer. after data transmission is complete, the parity bit will be stored in scxbuf in the 7-bit uart mode and scxmod0 in the 8-bit uart mode. the and settings must be completed before data is written to the transmit buffer. 10.6.2.2 receiving data if the received data is move d from the receive shift register to th e receive buffer, a parity is generated. in the 7-bit uart mode, the generated parity is compared with the parity stored in scxbuf, while in the 8-bit uart mode, it is compared with the one in scxcr. if there is any difference, a parity error occurs and the of the scxcr register is set to "1". in use of the fifo, indicates that a parity error was ge nerated in one of the received data. 10.6.3 stop bit length the length of the stop bit in the uart transmission mode can be selected from one bit or two bits by set- ting the scxmod2. the length of the stop bit da ta is determined as one-bit when it is received regardless of the setting of this bit.
page 10-21 TMPM372FWUG 2013/4/15 10.7 clock control 10.7.1 prescaler there is a 7-bit prescaler to divide a prescaler input clock t0 by 2, 8, 32 and 128. use the cgsyscr register in the clock/mode control block to select the input clock t0 of the prescaler. the prescaler becomes active only when the baud rate generator is selected as a transfer clock by scxmod0 = "01". table 10-4 show the resolution of the input clock to the baud rate generator.
page 10-22 10. serial channel (sio/uart) 10.7 clock control TMPM372FWUG 2013/4/15 table 10-4 clock resolution to the baud rate generator fc = 80 mhz peripheral clock selection cgsyscr clock gear value cgsyscr prescaler clock selection cgsyscr prescaler output clock resolution t1 t4 t16 t64 0 (fgear) 000 (fc) 000 (fperiph/1) fc/2 1 (0.025 s) fc/2 3 (0.1 s) fc/2 5 (0.4 s) fc/2 7 (1.6 s) 001 (fperiph/2) fc/2 2 (0.05 s) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) 010 (fperiph/4) fc/2 3 (0.1 s) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 011 (fperiph/8) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 100 (fperiph/16) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) fc/2 11 (25.6 s) 101 (fperiph/32) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) fc/2 12 (51.2 s) 100 (fc/2) 000 (fperiph/1) fc/2 2 (0.05 s) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) 001 (fperiph/2) fc/2 3 (0.1 s) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 010 (fperiph/4) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 011 (fperiph/8) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) fc/2 11 (25.6 s) 100 (fperiph/16) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) fc/2 12 (51.2 s) 101 (fperiph/32) fc/2 7 (1.6 s) fc/2 9 (6.4 s) fc/2 11 (25.6 s) fc/2 13 (102.4 s) 101 (fc/4) 000 (fperiph/1) fc/2 3 (0.1 s) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 001 (fperiph/2) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 010 (fperiph/4) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) fc/2 11 (25.6 s) 011 (fperiph/8) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) fc/2 12 (51.2 s) 100 (fperiph/16) fc/2 7 (1.6 s) fc/2 9 (6.4 s) fc/2 11 (25.6 s) fc/2 13 (102.4 s) 101 (fperiph/32) fc/2 8 (3.2 s) fc/2 10 (12.8 s) fc/2 12 (51.2 s) fc/2 14 (204.8 s) 110 (fc/8) 000 (fperiph/1) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 001 (fperiph/2) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) fc/2 11 (25.6 s) 010 (fperiph/4) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) fc/2 12 (51.2 s) 011 (fperiph/8) fc/2 7 (1.6 s) fc/2 9 (6.4 s) fc/2 11 (25.6 s) fc/2 13 (102.4 s) 100 (fperiph/16) fc/2 8 (3.2 s) fc/2 10 (12.8 s) fc/2 12 (51.2 s) fc/2 14 (204.8 s) 101 (fperiph/32) fc/2 9 (6.4 s) fc/2 11 (25.6 s) fc/2 13 (102.4 s) fc/2 15 (409.6 s) 111 (fc/16) 000 (fperiph/1) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) fc/2 11 (25.6 s) 001 (fperiph/2) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) fc/2 12 (51.2 s) 010 (fperiph/4) fc/2 7 (1.6 s) fc/2 9 (6.4 s) fc/2 11 (25.6 s) fc/2 13 (102.4 s) 011 (fperiph/8) fc/2 8 (3.2 s) fc/2 10 (12.8 s) fc/2 12 (51.2 s) fc/2 14 (204.8 s) 100 (fperiph/16) fc/2 9 (6.4 s) fc/2 11 (25.6 s) fc/2 13 (102.4 s) fc/2 15 (409.6 s) 101 (fperiph/32) fc/2 10 (12.8 s) fc/2 12 (51.2 s) fc/2 14 (204.8 s) fc/2 16 (819.2 s)
page 10-23 TMPM372FWUG 2013/4/15 note 1: the prescaler output clock tn must be selected so that the relationship " tn fsys / 2" is satisfied (so that tn is slower than fsys). note 2: do not change the clock gear while sio is operating. note 3: the dashes in the above table indicate that the setting is prohibited. 1 (fc) 000 (fc) 000 (fperiph/1) fc/2 1 (0.025 s) fc/2 3 (0.1 s) fc/2 5 (0.4 s) fc/2 7 (1.6 s) 001 (fperiph/2) fc/2 2 (0.05 s) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) 010 (fperiph/4) fc/2 3 (0.1 s) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 011 (fperiph/8) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 100 (fperiph/16) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) fc/2 11 (25.6 s) 101 (fperiph/32) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) fc/2 12 (51.2 s) 100 (fc/2) 000 (fperiph/1) ? fc/2 3 (0.1 s) fc/2 5 (0.4 s) fc/2 7 (1.6 s) 001 (fperiph/2) fc/2 2 (0.05 s) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) 010 (fperiph/4) fc/2 3 (0.1 s) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 011 (fperiph/8) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 100 (fperiph/16) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) fc/2 11 (25.6 s) 101 (fperiph/32) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) fc/2 12 (51.2 s) 101 (fc/4) 000 (fperiph/1) ? fc/2 3 (0.1 s) fc/2 5 (0.4 s) fc/2 7 (1.6 s) 001 (fperiph/2) ? fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) 010 (fperiph/4) fc/2 3 (0.1 s) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 011 (fperiph/8) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 100 (fperiph/16) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) fc/2 11 (25.6 s) 101 (fperiph/32) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) fc/2 12 (51.2 s) 110 (fc/8) 000 (fperiph/1) ? ? fc/2 5 (0.4 s) fc/2 7 (1.6 s) 001 (fperiph/2) ? fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) 010 (fperiph/4) ? fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 011 (fperiph/8) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 100 (fperiph/16) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) fc/2 11 (25.6 s) 101 (fperiph/32) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) fc/2 12 (51.2 s) 111 (fc/16) 000 (fperiph/1) ? ? fc/2 5 (0.4 s) fc/2 7 (1.6 s) 001 (fperiph/2) ? ? fc/2 6 (0.8 s) fc/2 8 (3.2 s) 010 (fperiph/4) ? fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 011 (fperiph/8) ? fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 100 (fperiph/16) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) fc/2 11 (25.6 s) 101 (fperiph/32) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) fc/2 12 (51.2 s) table 10-4 clock resolution to the baud rate generator fc = 80 mhz peripheral clock selection cgsyscr clock gear value cgsyscr prescaler clock selection cgsyscr prescaler output clock resolution t1 t4 t16 t64
page 10-24 10. serial channel (sio/uart) 10.7 clock control TMPM372FWUG 2013/4/15 10.7.2 serial clock generation circuit the serial clock circuit is a block to generate transmit and receive clocks (sioclk) and consists of the cir- cuits in which clocks can be se lected by the settings of the baud rates generator and modes. 10.7.2.1 baud rate generator the baud rate generator generates transmit and receive clocks to determine th e serial channel transfer rate. (1) baud rate generator input clock the input clock of the baud rate generator is selected from the prescaler outputs divided by 2, 8, 32 and 128. this input clock is selected by setting the scxbrcr. (2) baud rate generator output clock the frequency division ratio of th e output clock in the baud rate generator is set by scxbrcr and scxbradd. the following frequency divide ratios can be used; 1/n frequency division in the i/o interface mode ,either 1/n or n + (16-k)/16 in the uart mode. the table below shows the frequency division ratio which can be selected. note: 1/n (n = 1)frequency division ratio can be used only when a double buffer is enabled. mode divide function setting scxbrcr divide by n scxbrcr divide by k scxbradd i/o interface divide by n 1 to 16 (note) - uart divide by n 1 to 16 - n + (16-k)/16 division 2 to 15 1 to 15
page 10-25 TMPM372FWUG 2013/4/15 10.7.2.2 clock selection circuit a clock can be selected by set ting the modes and the register. modes can be specified by setting the scxmod0. the input clock in i/o interface mo de is selected by setting scx cr. the clock in uart mode is selected by setting scxmod0. (1) transfer clock in i/o interface mode table 10-5 shows clock sel ection in i/o interface mode. to get the highest baud rate, the baud rate generator must be set as below. note: when deciding clock settings, make sure that ac electrical character is satisfied. ? clock/mode control block settings - fc = 80mhz - fgear = 80mhz (cgsyscr = "000" : fc selected) - t0 = 80mhz (cgsyscr = "000" : 1 division ratio) ? sio settings (if double buffer is used) - clock (scxbrcr = "00" : t1 selected) = 40mhz - divided clock frequency (scxbrcr = "0001" : 1 division ratio) = 40mhz 1 division ratio can be selected if double buffer is used. in this case, baud rate is 20mbps because 40mhz is divided by 2. ? sio settings (if double buffer is not used) - clock (scxbrcr = "00" : t1 selected) = 40mhz - divided clock frequency (scxbrcr = "0010" : 2 division ratio) = 20mhz 2 division ratio is the highest if double buffer is not used. in this case, baud rate is 10mbps because 20mhz is divided by 2. to use sclk input, the following conditions must be satisfied. ? if double buffer is used - sclk cycle > 6/fsys the highest baud rate is less than 80 6 = 13.3 mbps. table 10-5 clock selection in i/o interface mode mode scxmod0 input/output selection scxcr clock edge selection scxcr clock of use i/o interface mode sclk output set to "0". (fixed to the rising edge) divided by 2 of the baud rate gen- erator output. sclk input rising edge sclk input rising edge falling edge sclk input falling edge
page 10-26 10. serial channel (sio/uart) 10.7 clock control TMPM372FWUG 2013/4/15 ? if double buffer is not used - sclk cycle > 8/fsys the highest baud rate is less than 80 8 = 10 mbps. (2) transfer clock in the uart mode table 10-6 shows the clock selection in the ua rt mode. in the uart mode, selected clock is divided by 16 in the receive counter or the transmit co unter before use. the examples of baud rate in each clock settings. ? if the baud rate generator is used - fc = 80mhz - fgear = 80mhz (cgsyscr = "000" : fc selected) - t0 = 80mhz (cgsyscr = "000" : 1 division ratio) -clock = t1 = 40mhz (scxbrcr = "00" : t1 selected) the highest baud rate is 2.5mbp s because 40mhz is divided by 16. table 10-7 shows examples of baud rate when the baud rate generator is used with the fol- lowing clock settings. ? fc = 9.8304mhz ? fgear = 9.8304mhz (cgsyscr = "000" : fc selected) ? t0 = 4.9152mhz (cgsyscr = "001" : 2 division ratio) ? if the sclk input is used table 10-6 clock selection in uart mode mode scxmod0 clock selection scxmod0 uart mode timer output baud rate generator fsys sclk input table 10-7 example of uart mode baud rate (using the baud rate generator) fc [mhz] division ratio n (scxbrcr) t1 (fc/4) t4 (fc/16) t16 (fc/64) t64 (fc/256) 9.830400 2 76.800 19.200 4.800 1.200 4 38.400 9.600 2.400 0.600 8 19.200 4.800 1.200 0.300 16 9.600 2.400 0.600 0.150 unit kbps
page 10-27 TMPM372FWUG 2013/4/15 to use sclk input, the following conditions must be satisfied. - sclk cycle > 2/fsys the highest baud rate must be less than 80 2 16 = 2.5 mbps. ? if fsys is used since the highest value of fsys is 80mhz, the highest baud rate is 80 16 = 5mbps. ? if timer output is used to enable the timer output, the following condition must be set: a timer flip-flop output inverts when the value of the counter and th at of tbxrg1 match. the sioclk clock fre- quency is "setting value of tbxrg1 2". baud rates can be obtained by using the following formula. table 10-8 shows the examples of baud rates when the timer output is used with the follow- ing clock settings. ? fc = 80mhz / 9.8304mhz / 8mhz ? fgear = 80mhz / 9.8304mhz / 8mhz (cgsyscr = "000" : fc selected) ? t0 = 40mhz / 4.9152mhz / 4mhz (cgsyscr = "001" : 2 division ra- tio) ? timer count clock = 4mhz / 1.2287mhz / 1mhz (tbxmod = "01" : t1 selected) table 10-8 example of uart mode baud rate (using the timer output) tbxrg0 setting fc 80mhz 9.8304mhz 8mhz 0x0001 625 76.8 62.5 0x0002 312.5 38.4 31.25 0x0003 - 25.6 - 0x0004 156.25 19.2 15.625 0x0005 125 15.36 12.5 0x0006 - 12.8 - 0x0008 78.125 9.6 - 0x000a 62.5 7.68 6.25 0x0010 39.025 4.8 - 0x0014 31.25 3.84 3.125 unit kbps baud rate calculation transfer rate = clock frequency selected by cgsyscr (tbxrg1 2) 2 16 in the case the timer prescaler clock t1 (2divition ratio) is selected. one clock cycle is a period that the timer flip-flop is inverted twice.
page 10-28 10. serial channel (sio/uart) 10.8 transmit/receive buffer and fifo TMPM372FWUG 2013/4/15 10.8 transmit/receive buffer and fifo 10.8.1 configuration figure 10-3 shows the configuration of transmit buffer, receive buffer and fifo. appropriate settings are required for using buffer an d fifo. the configuration may be predefined depending on the mode. figure 10-3 the configur ation of buffer and fifo 10.8.2 transmit/receive buffer transmit buffer and receive buffer are double-bu ffered. the buffer configuration is specified by scxmod2. in the case of using a receive buffer, if sclk input is set to generate clock output in the i/o interface mode or the uart mode is selected, it?s double buffered desp ite the settings. in other modes, it?s accord- ing to the settings. table 10-9 shows correlation between modes and buffers. table 10-9 mode and buffer composition mode scxmod2 "0" "1" uart transmit single double receive double double i/o interface (sclk input) transmit single double receive double double i/o interface (sclk output) transmit single double receive single double 6tcpuokv(+(1 6tcpuokvdwhhgt 6tcpuokvujkhvtgikuvgt 6:& 4gegkxg (+(1 (ktuvuvcig 5geqpfuvcig 6jktfuvcig (qwtvjuvcig 4gegkxgdwhhgt 4gegkxgujkhvtgikuvgt 4:& (ktuvuvcig 5geqpfuvcig 6jktfuvcig (qwtvjuvcig
page 10-29 TMPM372FWUG 2013/4/15 10.8.3 fifo in addition to the double buffer function above described, 4-byte fifo can be used. to enable fifo, enable the doubl e buffer by setting scxmod2 to "1" and scxfcnf to "1". the fifo buffer co nfiguration is specified by scxmod1. note:to use tx/rx fifo buffer, tx/rx fifo must be clea red after setting the sio transfer mode (half duplex/full duplex) and enabling fifo (scxfcnf = "1"). table 10-10 shows correlation between modes and fifo. 10.9 status flag the scxmod2 register has two types of flag. this bit is significant only when the double buffer is enabled. is a flag to show that the receive buffer is fu ll. when one frame of data is received and the data is moved from the receive shift register to the receive buffers, this bit cha nges to "1" while reading this bit changes it to "0". shows that the transmit buffers are empty. when data in the tran smit buffers is moved to the transmit shift register, this bit is set to "1" . when data is set to the transmit buffers, the bit is cleared to "0". 10.10error flag three error flags are provided in th e scxcr register. the meaning of the flags is changed depending on the modes. the table below shows the meanings in each mode. these flags are cleared to "0" af ter reading the scxcr register. table 10-10 mode and fifo composition scxmod1 rx fifo tx fifo half duplex rx "01" 4byte - half duplex tx "10" - 4byte full duplex "11" 2byte 2byte mode flag uart overrun error parity error framing error i/o interface (sclk input) overrun error underrun error (when using double buffer or fifo) fixed to 0 fixed to 0 (when a double buffer and fifo unused) i/o interface (sclk output) undefined undefined fixed to 0
page 10-30 10. serial channel (sio/uart) 10.10 error flag TMPM372FWUG 2013/4/15 10.10.1oerr flag in both uart and i/o interface modes, this bit is set to "1" when an error is generated by completing the reception of the next frame of receive data before th e receive buffer has been read. if the receive fifo is enabled, the received data is automa tically moved to the receive fifo a nd no overrun error will be generated until the receive fifo is full (or until the usable bytes are fully occupied). in the i/o interface with sclk output mode, the sclk output stops upon setting the flag. note:to switch the i/o interface sclk output mode to ot her modes, read the scxcr register and clear the overrun flag. 10.10.2perr flag this flag indicates a parity error in the uart mo de and an under-run error in the i/o interface mode. in the uart mode, is set to "1" when the pari ty generated from the received data is different from the parity received. in the i/o interface mode, is set to "1" u nder the following conditions when a double buffer is enabled. in the sclk input mode, is set to "1" when the sclk is input after completing data output of the transmit shift register with no data in the transmit buffer. in the sclk output mode, is set to "1" after completing output of all data and the sclk output stops. note:to switch the i/o interface sclk output mode to other modes, read the scxcr register and clear the under- run flag. 10.10.3ferr flag a framing error is generated if the corresponding stop bit is determined to be "0" by sampling the bit at around the center. regardless of the stop bit length settings in the scxmod2register, the stop bit status is determined by only 1. this bit is fixed to "0" in the i/o interface mode.
page 10-31 TMPM372FWUG 2013/4/15 10.11receive 10.11.1receive counter the receive counter is a 4-bit binary counter and is up-counted by sioclk. in the uart mode, sixteen sioclk clock pulses are used in r eceiving a single data bit and the data symbol is sampled at the seventh, eighth, and ninth pulses. from these three samples, majority logi c is applied to decide the received data. 10.11.2receive control unit 10.11.2.1i/o interface mode in the sclk output mode with scxcr set to "0", the rxd pin is sampled on the rising edge of the shift clock outputted to the sclk pin. in the sclk input mode wi th scxcr set to "1", the serial receive data rxd pin is sampled on the rising or falling edge of sclk input signal depending on the scxcr setting. 10.11.2.2uart mode the receive control unit has a start bit detection circuit, which is used to initiate receive operation when a normal start bit is detected. 10.11.3receive operation 10.11.3.1receive buffer the received data is stored by 1 bit in the receive sh ift register. when a comple te set of bits has been stored, the interrupt intrxx is generated. when the double buffer is enabled, the data is mo ved to the receive buffer (scxbuf) and the receive buffer full flag (scxmod2< rbfll>) is set to "1". the receive buffe r full flag is "0" cleared by reading the receive buffer. the receive buffer full flag does not have any value for the single buffer. figure 10-4 receive buffer operation data 1 data 1 receive shift register receive buffer scxmod2 receive interrupt(intrxx) receive buffer read
page 10-32 10. serial channel (sio/uart) 10.11 receive TMPM372FWUG 2013/4/15 10.11.3.2receive fifo operation when fifo is enabled, the received data is moved from receive buffer to r eceive fifo and the receive buffer full flag is cleared immediately. an inte rrupt will be generated acco rding to the scxrfc setting. note: when the data with parity bit are received in ua rt mode by using the fifo, the parity error flag is shown the occurring the parity error in the received data. the following describes configurations and operations in the half duplex rx mode. after setting of the above fifo co nfiguration, the data reception is started by writ ing "1" to the scxmod0 . when the data is stored all in the receive shift register, receive buffer and receive fifo, scxmod0 is automatically clear ed and the receive operation is finished. in this above condition, if the co ntinuous reception afte r reaching the fill level is enabled, and it is pos- sible to receive a data continuously wi th and reading the data in the fifo. figure 10-5 receive fifo operation scxmod1[6:5] = 01 : transfer mode is set to half duplex mode scxfcnf[4:0] = 10111 : automatically inhibits continuous reception after reaching the fill level. : the number of bytes to be used in the receive fifo is the same as the interrupt generation fill level. scxrfc[1:0] = 00 : the fill level of fifo in which generated receive interrupt is set to 4-byte. scxrfc[7:6] = 11 : clears receive fifo and sets the condition of interrupt generation. receive shift register receive buffer scxmod2 rx interrupt (intrxx) rx fifo the first stage the second stage the third stage the fourth stage scxmod0 data1 data1 data2 data2 data1 data3 data2 data1 data3 data4 data2 data1 data3 data4 data2 data1 data3 data4 data1 data2 data1 data3 data2 data4 data3 data4 data5 data5 data5 data6
page 10-33 TMPM372FWUG 2013/4/15 10.11.3.3i/o interface mode with sclk output in the i/o interface mode and sclk output setting, sc lk output stops when all received data is stored in the receive buffer and fifo. so, in this mode, the overrun error flag has no meaning. the timing of sclk output stop and re-out put depends on receive buffer and fifo. (1) case of single buffer stop sclk output after receiving a data. in this mode, i/o interface can transf er each data with the transfer device by hand-shake. when the data in a buffer is read, sclk output is restarted. (2) case of double buffer stop sclk output after receiving the data into a receive shift register and a receive buffer. when the data is read, sclk output is restarted. (3) case of fifo stop sclk output after receiving the data into a shift register, r eceived buffer and fifo. when one byte data is read, the data in the recei ved buffer is transferred into fifo and the data in the receive shift register is transferred into received buffer and sclk output is restarted. and if scxfcnf is set to "1", sclk stops and receive opera tion stops with clear- ing scxmod0 bit too. 10.11.3.4read received data in spite of enabling or disabling fifo, read the received data from the receive buffer (scxbuf). when receive fifo is disabled, the buffer full flag scxmod2 is cleared to "0" by this read- ing. in the case of the next data can be received in th e receive shift register befo re reading a data from the receive buffer. the parity bit to be added in the 8-bit uart mode as we ll as the most significant bit in the 9-bit uart mode will be stored in scxcr. when the receive fifo is available, the 9-bit uart mode is prohibited because up to 8-bit data can be stored in fifo. in the 8-bit uart mode, the parity bit is lost but parity error is determined and the result is stored in scxcr. 10.11.3.5wake-up function in the 9-bit uart mode, the slave controller can be operated in the wake-up mode by setting the wake- up function scxmod0 to "1." in this case, the interrupt intrxx will be generated only when scxcr is set to "1."
page 10-34 10. serial channel (sio/uart) 10.11 receive TMPM372FWUG 2013/4/15 10.11.3.6overrun error when fifo is disabled, the overrun error is occurred a nd set overrun flag without completing data read before receiving the next data. when overrun error is occurred, a content of receive buffer and scxcr is not lost, but a content of receive shift register is lost. when fifo is enabled, overrun er ror is occurred and set overrun fl ag by no reading the data before moving the next data into received buff er when fifo is full. in this case, the content of fifo are not lost. in the i/o interface mode with sclk output setting, the clock output automati cally stops, so this flag has no meaning. note: when the mode is changed from i/o interface sclk output mode to the other mode, read scxcr and clear overrun flag.
page 10-35 TMPM372FWUG 2013/4/15 10.12transmission 10.12.1transmission counter the transmit counter is a 4-bit binary counter and is counted by sioclk as in the case of the receive counter. in uart mode, it generates a transmit clock (txdclk) on every 16th clock pulse. figure 10-6 generation of transmission clock 10.12.2transmission control 10.12.2.1i/o interface mode in the sclk output mode with scxcr set to "0 ", each bit of data in the transmit buffer is out- putted to the txd pin on the falling edge of the shift clock outputted from the sclk pin. in the sclk input mode with scxcr set to "1 ", each bit of data in the transmit buffer is output- ted to the txd pin on the rising or falling edge of the sclk input signal according to the scxcr setting. 10.12.2.2uart mode when the transmit data is written in the transmit buffer, data transmission is initiated on the rising edge of the next txdclk and the transmit shift clock signal is also generated. 10.12.3transmit operation 10.12.3.1operation of transmission buffer if double buffering is disabled, the cpu writes data only to transmit shift register and the transmit interrupt inttxx is generated upon completion of data transmission. if double buffering is enabled (including the case the transmit fifo is enabled), data written to the transmit buffer is moved to the transmit shift register. the inttxx interrupt is generated at the same time and the transmit buffer empty flag (scxmod2) is set to "1". this flag indicates that the next transmit data can be written. when the next data is written to the transmit buffer, the flag is cleared to "0". 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 sioclk txdclk
page 10-36 10. serial channel (sio/uart) 10.12 transmission TMPM372FWUG 2013/4/15 figure 10-7 operation of transmission buffer (double-buffer is enabled) 10.12.3.2transmit fifo operation when fifo is enabled, the maximum 5-byte data can be stored using the tr ansmit buffer and fifo. once transmission is enabled, data is transferred to the transmit shift register from the transmit buffer and start transmission. if data exists in the fifo, the da ta is moved to the transmit buffer immediately, and the flag is cleared to "0". note: to use tx fifo buffer, tx fifo must be cleared after setting the sio transfer mode (half duplex/ full duplex) and enabling fifo (scxfcnf = "1"). settings and operations to transmit 4-byte data stream by setting the transfer mode to half duplex are shown as below. after above settings are configured, data transmission can be initiated by writing 5 bytes of data to the transmit buffer and fifo, and setting the scxmod1 bit to "1". when the last transmit data is moved to the transmit buffer, the transmit fifo interrupt is generated. when transmission of the last data is completed, the transmissi on sequence is terminated. once above settings are configured, if the transmissi on is not set as auto disabled, the transmission should lasts by writing transmit data. scxmod1[6:5] = 10 : transfer mode is set to half duplex. scxfcnf[4:0] = 11011 : transmission is automatically disabled if fifo becomes empty. the number of bytes to be used in the receive fifo is the same as the interrupt generation fill level. scxtfc[1:0] = 00 : sets the interrupt generation fill level to "0". scxtfc[7:6] = 11 : clears receive fifo and sets the condition of interrupt generation. scxfcnf[0] = 1 : enable fifo. data 1 transmit buffer scxmod2 transmit interrupt(inttxx) write data data 2 data 1 transmit shift register
page 10-37 TMPM372FWUG 2013/4/15 10.12.3.3i/o interface mode/transmission by sclk output if sclk is set to generate clock the i/o interface mode, the sclk output automatically stops when all data transmission is completed and underrun error will not occur. the timing of suspension and resume of sclk output is different depending on the buffer and fifo usage. (1) single buffer the sclk output stops each time one frame of data is transferred. handshaking for each data with the other side of communication can be enabled. the sclk output resumes when the next data is written in the buffer. (2) double buffer the sclk output stops upon completion of data transmission of the transmit shift register and the transmit buffer. the sclk output resumes when the next data is written in the buffer. (3) fifo the transmission of all data stor ed in the transmit shift register, transmit buffer and fifo is com- pleted, the sclk output stops. the next data is written, sclk output resumes. if scxfcnf is configured, scxmod0< txe> bit is cleared at the same time as sclk stop and the transmission stops. transmit fifo fourth stage scxmod2 data 5 transmit buffer transmit shift register transmit interrupt(inttxx) scxmod1 third stage second stage first stage data 4 data 3 data 2 data 1 data 5 data 4 data 3 data 2 data 5 data 4 data 3 data 1 data 2 data 3 data 5 data 4 data 5 data 4 data 5
page 10-38 10. serial channel (sio/uart) 10.12 transmission TMPM372FWUG 2013/4/15 10.12.3.4under-run error if the transmit fifo is disabled in the i/o interface sclk input mode an d if no data is set in transmit buffer before the next frame clock input, which occurs upon completion of data transmission from trans- mit shift register, an under-run error occurs and scxcr is set to "1". in the i/o interface mode with sclk output setting, the clock output automati cally stops, so this flag has no meaning. note: before switching the i/o interface sclk output mode to other modes, read the scxcr register and clear the underrun flag.
page 10-39 TMPM372FWUG 2013/4/15 10.13handshake function the function of the handshake is to enable frame-by-frame data transmission by using the cts (clear to send) pin and to prevent overrun errors. this function can be enabled or disabled by scxmod0. when the cts pin is set to "high" level, the current data tran smission can be completed but the next data transmis- sion is suspended until the cts pin returns to the "low" level. however in this case, the inttxx interrupt is gener- ated in the normal timing, the next tran smit data is written in the transmit buffer, and it waits until it is ready to transmit data. note 1: if the cts signal is set to "h" during transmission, the next data transmission is suspended after the current trans- mission is completed.(point "a" in figure 10-9) note 2: data transmission starts on the first falling edge of the txdclk clock after cts is set to "l". (point "b" in figure 10-9) although no rts pin is provided, a handshake control function can easily implemented by assigning one bit of the port for the rts function. by setting the port to "high" level upon completion of da ta reception (in th e receive inter- rupt routine), the transmit side can be requested to suspend data transmission. figure 10-8 h andshake function figure 10-9 cts signal timing txd cts rxd rts (any port) transmit side receive side transmission is suspended during this period. start bit bit 0 txd sioclk data write to transmit buffer or shift register txdclk cts 13 14 15 16 1 2 3 14 15 16 1 2 3 a b
page 10-40 10. serial channel (sio/uart) 10.14 interrupt/error generation timing TMPM372FWUG 2013/4/15 10.14interrupt/erro r generation timing 10.14.1rx interrupts figure 10-10 shows the data flow of receive operation and the route of read. figure 10-10 receive buffer /fifo configuration diagram 10.14.1.1single buffer / double buffer rx interrupts are generated at the time depends on the transfer mode and th e buffer configurations, which are given as follows. note: interrupts are not generated when an overrun error is occurred. 10.14.1.2fifo in use of fifo, receive interrupt is generated on the condition that the followi ng either operation and scxrfc setting are established. ? reception completion of all bits of one frame. ? reading fifo interrupt conditions are decided by the scxrfc settings as described in table 10-11. buffer configurations uart modes io interface modes single buffer ? immediately after the rising / falling edge of the last sclk (rising or falling is determined according to scxcr setting.) double buffer around the center of the first stop bit immediately after the rising / falling edge of the last sclk (rising or falling is determined according to scxcr

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